Discussion:
Cache enabling
(too old to reply)
Pranshu Kalra
2016-12-05 09:25:04 UTC
Permalink
So I was running a PARSEC benchmark on an ARM system with 4 cores. I ran
the benchmark without any caches enabled. Then I enabled the L1 cache. In
both the cases my execution time came out to be unchanged. I tried changing
the associativity, the cache size. But the execution time still remains
constant. Can anybody tell me what I am missing here?

Pranshu Kalra
B.E(Hons) Electrical and Electronics
Birla Institute of Technology and Science, Pilani
Ph : +91 7597634875
Jason Lowe-Power
2016-12-05 14:48:22 UTC
Permalink
Hi Pranshu,

Are you using a timing CPU model (TimingSimpleCPU, MinorCPU, or
DerivO3CPU)? Also, you should read the python config file code carefully
and make sure that it is generating the system you are expecting (e.g.,
when you don't have caches enable there actually aren't any caches). You
can also look at m5out/config.ini to see the exact system you simulated.

Jason

On Mon, Dec 5, 2016 at 4:42 AM Pranshu Kalra <
Post by Pranshu Kalra
So I was running a PARSEC benchmark on an ARM system with 4 cores. I ran
the benchmark without any caches enabled. Then I enabled the L1 cache. In
both the cases my execution time came out to be unchanged. I tried changing
the associativity, the cache size. But the execution time still remains
constant. Can anybody tell me what I am missing here?
Pranshu Kalra
B.E(Hons) Electrical and Electronics
Birla Institute of Technology and Science, Pilani
Ph : +91 7597634875 <+91%2075976%2034875>
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Andreas Hansson
2016-12-05 15:23:44 UTC
Permalink
Or even better: make sure you have pydot installed and you will get a graphical representation of the system topology. Just have a look at config.dot.svg or config.dot.pdf

Andreas

From: gem5-users <gem5-users-***@gem5.org<mailto:gem5-users-***@gem5.org>> on behalf of Jason Lowe-Power <***@lowepower.com<mailto:***@lowepower.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Monday, 5 December 2016 at 14:48
To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Cache enabling

Hi Pranshu,

Are you using a timing CPU model (TimingSimpleCPU, MinorCPU, or DerivO3CPU)? Also, you should read the python config file code carefully and make sure that it is generating the system you are expecting (e.g., when you don't have caches enable there actually aren't any caches). You can also look at m5out/config.ini to see the exact system you simulated.

Jason

On Mon, Dec 5, 2016 at 4:42 AM Pranshu Kalra <***@pilani.bits-pilani.ac.in<mailto:***@pilani.bits-pilani.ac.in>> wrote:
So I was running a PARSEC benchmark on an ARM system with 4 cores. I ran the benchmark without any caches enabled. Then I enabled the L1 cache. In both the cases my execution time came out to be unchanged. I tried changing the associativity, the cache size. But the execution time still remains constant. Can anybody tell me what I am missing here?

Pranshu Kalra
B.E(Hons) Electrical and Electronics
Birla Institute of Technology and Science, Pilani
Ph : +91 7597634875<tel:+91%2075976%2034875>








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Pranshu Kalra
2016-12-06 00:21:53 UTC
Permalink
Hi Jason,
I'm new to the software and don't really know where to check in the config
file about the cache connectivity. Can you help me out on that front a bit
more?




Pranshu Kalra
B.E(Hons) Electrical and Electronics
Birla Institute of Technology and Science, Pilani
Ph : +91 7597634875
Post by Jason Lowe-Power
Hi Pranshu,
Are you using a timing CPU model (TimingSimpleCPU, MinorCPU, or
DerivO3CPU)? Also, you should read the python config file code carefully
and make sure that it is generating the system you are expecting (e.g.,
when you don't have caches enable there actually aren't any caches). You
can also look at m5out/config.ini to see the exact system you simulated.
Jason
Post by Pranshu Kalra
So I was running a PARSEC benchmark on an ARM system with 4 cores. I ran
the benchmark without any caches enabled. Then I enabled the L1 cache. In
both the cases my execution time came out to be unchanged. I tried changing
the associativity, the cache size. But the execution time still remains
constant. Can anybody tell me what I am missing here?
Pranshu Kalra
B.E(Hons) Electrical and Electronics
Birla Institute of Technology and Science, Pilani
Ph : +91 7597634875 <+91%2075976%2034875>
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Jason Lowe-Power
2016-12-06 15:14:26 UTC
Permalink
Hi Pranshu,

m5out/config.ini is the file you want to look at. Or, as Andreas suggests,
you can look at m5out/config.dot.pdf if you have pydot installed.

You may benefit from going through the tutorial/book I'm working on:
http://learning.gem5.org.

Jason

On Mon, Dec 5, 2016 at 6:22 PM Pranshu Kalra <
Post by Pranshu Kalra
Hi Jason,
I'm new to the software and don't really know where to check in the config
file about the cache connectivity. Can you help me out on that front a bit
more?
Pranshu Kalra
B.E(Hons) Electrical and Electronics
Birla Institute of Technology and Science, Pilani
Ph : +91 7597634875 <+91%2075976%2034875>
Hi Pranshu,
Are you using a timing CPU model (TimingSimpleCPU, MinorCPU, or
DerivO3CPU)? Also, you should read the python config file code carefully
and make sure that it is generating the system you are expecting (e.g.,
when you don't have caches enable there actually aren't any caches). You
can also look at m5out/config.ini to see the exact system you simulated.
Jason
On Mon, Dec 5, 2016 at 4:42 AM Pranshu Kalra <
So I was running a PARSEC benchmark on an ARM system with 4 cores. I ran
the benchmark without any caches enabled. Then I enabled the L1 cache. In
both the cases my execution time came out to be unchanged. I tried changing
the associativity, the cache size. But the execution time still remains
constant. Can anybody tell me what I am missing here?
Pranshu Kalra
B.E(Hons) Electrical and Electronics
Birla Institute of Technology and Science, Pilani
Ph : +91 7597634875 <+91%2075976%2034875>
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Pranshu Kalra
2016-12-06 23:02:31 UTC
Permalink
Hi,
Thanks for the help. Its working now. I need help with changing the cache
replacement policy from LRU to Random Replacement though. Can you help me
out with that??

Pranshu Kalra
B.E(Hons) Electrical and Electronics
Birla Institute of Technology and Science, Pilani
Ph : +91 7597634875
Post by Jason Lowe-Power
Hi Pranshu,
m5out/config.ini is the file you want to look at. Or, as Andreas suggests,
you can look at m5out/config.dot.pdf if you have pydot installed.
http://learning.gem5.org.
Jason
Post by Pranshu Kalra
Hi Jason,
I'm new to the software and don't really know where to check in the
config file about the cache connectivity. Can you help me out on that front
a bit more?
Pranshu Kalra
B.E(Hons) Electrical and Electronics
Birla Institute of Technology and Science, Pilani
Ph : +91 7597634875 <+91%2075976%2034875>
Hi Pranshu,
Are you using a timing CPU model (TimingSimpleCPU, MinorCPU, or
DerivO3CPU)? Also, you should read the python config file code carefully
and make sure that it is generating the system you are expecting (e.g.,
when you don't have caches enable there actually aren't any caches). You
can also look at m5out/config.ini to see the exact system you simulated.
Jason
On Mon, Dec 5, 2016 at 4:42 AM Pranshu Kalra <
So I was running a PARSEC benchmark on an ARM system with 4 cores. I ran
the benchmark without any caches enabled. Then I enabled the L1 cache. In
both the cases my execution time came out to be unchanged. I tried changing
the associativity, the cache size. But the execution time still remains
constant. Can anybody tell me what I am missing here?
Pranshu Kalra
B.E(Hons) Electrical and Electronics
Birla Institute of Technology and Science, Pilani
Ph : +91 7597634875 <+91%2075976%2034875>
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Jason Lowe-Power
2016-12-08 20:31:27 UTC
Permalink
Hi Pranshu,

You want to change the tags parameter of the cache. See
src/mem/cache/Cache.py
tags = Param.BaseTags(LRU(), "Tag store (replacement policy)")
You can change this in the Python config files in configs/. If you are
using se.py/fs.py you can modify configs/common/CacheConfig.py.

You shouldn't be afraid of writing your own python script to configure
gem5. IMO, the interface to gem5 is not the command line, but the python
config files.

Jason

On Tue, Dec 6, 2016 at 5:02 PM Pranshu Kalra <
Hi,
Thanks for the help. Its working now. I need help with changing the cache
replacement policy from LRU to Random Replacement though. Can you help me
out with that??
Pranshu Kalra
B.E(Hons) Electrical and Electronics
Birla Institute of Technology and Science, Pilani
Ph : +91 7597634875 <+91%2075976%2034875>
Hi Pranshu,
m5out/config.ini is the file you want to look at. Or, as Andreas suggests,
you can look at m5out/config.dot.pdf if you have pydot installed.
http://learning.gem5.org.
Jason
On Mon, Dec 5, 2016 at 6:22 PM Pranshu Kalra <
Hi Jason,
I'm new to the software and don't really know where to check in the config
file about the cache connectivity. Can you help me out on that front a bit
more?
Pranshu Kalra
B.E(Hons) Electrical and Electronics
Birla Institute of Technology and Science, Pilani
Ph : +91 7597634875 <+91%2075976%2034875>
Hi Pranshu,
Are you using a timing CPU model (TimingSimpleCPU, MinorCPU, or
DerivO3CPU)? Also, you should read the python config file code carefully
and make sure that it is generating the system you are expecting (e.g.,
when you don't have caches enable there actually aren't any caches). You
can also look at m5out/config.ini to see the exact system you simulated.
Jason
On Mon, Dec 5, 2016 at 4:42 AM Pranshu Kalra <
So I was running a PARSEC benchmark on an ARM system with 4 cores. I ran
the benchmark without any caches enabled. Then I enabled the L1 cache. In
both the cases my execution time came out to be unchanged. I tried changing
the associativity, the cache size. But the execution time still remains
constant. Can anybody tell me what I am missing here?
Pranshu Kalra
B.E(Hons) Electrical and Electronics
Birla Institute of Technology and Science, Pilani
Ph : +91 7597634875 <+91%2075976%2034875>
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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