Amir Alipour
2018-06-28 10:53:19 UTC
Hey there fine developers of Gem5,
So I asked a question a while ago, about implementing a new cpu model in
gem5.
I'm still in that road and I have came up with a scenario to do the job.
However, I'm not sure if its following the standards of GEM5.
So the first steps of the scenario is:
1_ I define my base CPU model as a MemObject. This CPU model of mine does
not take instructions and doesn't know any threads. So I thought, instead
of inheriting form BaseCPU, I start from MemObject.
2_ Within this CPU model of mine, I have several components. Some of these
components are: Scheduler, Router (local), Controller, An SRAM to save some
internal configuration parameters and a Functional Block, which does the
computation.
To ease the process of implementation, I decided the define these
components, each as a ClockedObject. *** Now here I am not sure if I am
doing this right. Point is, each of these components see 1 or some other
specific components within the cpu model. For instance, Scheduler sees the
Controller, and controller sees the Functional Block. Controller Also sees
the scheduler to send some feedback messages. *** My questions would be:
_ Q) If I should define them as memObjects instead of ClockedObject, and
use the Master and Slave ports to connect them to eachother ? Or just go
with clockedObject and just save references within each component to be
able to communicate ?
_ Q) In general, what is the benefit of using Master and Slave ports ?
_ Q) For the SRAM that I'm about to insert in the cpu model, since its very
much like cache designs of conventional cpu models, should I just use one
of the already implemented cache models ?
_ Q) In case if finally decide to implement the SRAM, should I define it as
a Memobject ? or just go with BaseCache ?
3_ I'd then associate each component within the CPU model class.
I'm also going to implement all of the CPUs behavior within the CPU model
class, does this disturb GEM5's standards ? (Consider this a small project
just to implement the behavior of a non-conventional CPU model)
I know its a lot of question, and I'd appreciate any help I can get from
you guys ALOT!
Thank you so much.
Best,
Amir
So I asked a question a while ago, about implementing a new cpu model in
gem5.
I'm still in that road and I have came up with a scenario to do the job.
However, I'm not sure if its following the standards of GEM5.
So the first steps of the scenario is:
1_ I define my base CPU model as a MemObject. This CPU model of mine does
not take instructions and doesn't know any threads. So I thought, instead
of inheriting form BaseCPU, I start from MemObject.
2_ Within this CPU model of mine, I have several components. Some of these
components are: Scheduler, Router (local), Controller, An SRAM to save some
internal configuration parameters and a Functional Block, which does the
computation.
To ease the process of implementation, I decided the define these
components, each as a ClockedObject. *** Now here I am not sure if I am
doing this right. Point is, each of these components see 1 or some other
specific components within the cpu model. For instance, Scheduler sees the
Controller, and controller sees the Functional Block. Controller Also sees
the scheduler to send some feedback messages. *** My questions would be:
_ Q) If I should define them as memObjects instead of ClockedObject, and
use the Master and Slave ports to connect them to eachother ? Or just go
with clockedObject and just save references within each component to be
able to communicate ?
_ Q) In general, what is the benefit of using Master and Slave ports ?
_ Q) For the SRAM that I'm about to insert in the cpu model, since its very
much like cache designs of conventional cpu models, should I just use one
of the already implemented cache models ?
_ Q) In case if finally decide to implement the SRAM, should I define it as
a Memobject ? or just go with BaseCache ?
3_ I'd then associate each component within the CPU model class.
I'm also going to implement all of the CPUs behavior within the CPU model
class, does this disturb GEM5's standards ? (Consider this a small project
just to implement the behavior of a non-conventional CPU model)
I know its a lot of question, and I'd appreciate any help I can get from
you guys ALOT!
Thank you so much.
Best,
Amir