Discussion:
Increasing cacheline size in gem5
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Saivarun R
2018-01-29 14:42:38 UTC
Permalink
Hi everyone,

I'm trying to simulate a *DRAM caches*, in gem5, which are primarily
modeled as page-based caches in the research community. But the gem5
simulator only supports a maximum of *128 bytes* as the size of the
cacheline. I've seen the previous mailing lists in search of the answer,
but found nothing that would help me.

What is the best solution regarding this issue??

Thank you in advance :-)
Varun
Jason Lowe-Power
2018-01-29 21:09:39 UTC
Permalink
Hi Vaurn,

Three quick answers:
1. Currently, the cache line size in gem5 is global to the system. So you
can't have a different line size in some caches than others.
2. You could probably modify the code to increase the maximum cache block
size. I'm not sure why it's 128 bytes...
3. What I would do is *not* use the cache line size parameter for the DRAM
cache, but make your own new parameter. Basically treat the the DRAM cache
as a memory object that accepts 64 byte requests but stores data with a
different line size.

Hope this helps.

Jason

-----------
Jason Lowe-Power
Assistant Professor, Computer Science Department
University of California, Davis
3049 Kemper Hall
https://faculty.engineering.ucdavis.edu/lowepower/
Post by Saivarun R
Hi everyone,
I'm trying to simulate a *DRAM caches*, in gem5, which are primarily
modeled as page-based caches in the research community. But the gem5
simulator only supports a maximum of *128 bytes* as the size of the
cacheline. I've seen the previous mailing lists in search of the answer,
but found nothing that would help me.
What is the best solution regarding this issue??
Thank you in advance :-)
Varun
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Saivarun R
2018-01-30 06:37:07 UTC
Permalink
Hi Jason,

Thank you for you reply.
What you are suggesting is to model the Dram Cache similar to a memory
object, say main memory which takes requests of 64 bytes but stores at a
different granularity. Can you direct me as to where do I need to look for
this change??

Also is making cacheline size local to each cache is difficult to update??
Please share your views as to which one would be a better option to go
ahead.

Thank you
Varun
Post by Jason Lowe-Power
Hi Vaurn,
1. Currently, the cache line size in gem5 is global to the system. So you
can't have a different line size in some caches than others.
2. You could probably modify the code to increase the maximum cache block
size. I'm not sure why it's 128 bytes...
3. What I would do is *not* use the cache line size parameter for the DRAM
cache, but make your own new parameter. Basically treat the the DRAM cache
as a memory object that accepts 64 byte requests but stores data with a
different line size.
Hope this helps.
Jason
-----------
Jason Lowe-Power
Assistant Professor, Computer Science Department
University of California, Davis
3049 Kemper Hall
https://faculty.engineering.ucdavis.edu/lowepower/
Post by Saivarun R
Hi everyone,
I'm trying to simulate a *DRAM caches*, in gem5, which are primarily
modeled as page-based caches in the research community. But the gem5
simulator only supports a maximum of *128 bytes* as the size of the
cacheline. I've seen the previous mailing lists in search of the answer,
but found nothing that would help me.
What is the best solution regarding this issue??
Thank you in advance :-)
Varun
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Jason Lowe-Power
2018-01-31 01:22:51 UTC
Permalink
See dram_ctrl.cc for an example:
https://gem5.googlesource.com/public/gem5/+/master/src/mem/dram_ctrl.cc

Jason
Post by Saivarun R
Hi Jason,
Thank you for you reply.
What you are suggesting is to model the Dram Cache similar to a memory
object, say main memory which takes requests of 64 bytes but stores at a
different granularity. Can you direct me as to where do I need to look for
this change??
Also is making cacheline size local to each cache is difficult to update??
Please share your views as to which one would be a better option to go
ahead.
Thank you
Varun
Post by Jason Lowe-Power
Hi Vaurn,
1. Currently, the cache line size in gem5 is global to the system. So you
can't have a different line size in some caches than others.
2. You could probably modify the code to increase the maximum cache block
size. I'm not sure why it's 128 bytes...
3. What I would do is *not* use the cache line size parameter for the
DRAM cache, but make your own new parameter. Basically treat the the DRAM
cache as a memory object that accepts 64 byte requests but stores data with
a different line size.
Hope this helps.
Jason
-----------
Jason Lowe-Power
Assistant Professor, Computer Science Department
University of California, Davis
3049 Kemper Hall
https://faculty.engineering.ucdavis.edu/lowepower/
Post by Saivarun R
Hi everyone,
I'm trying to simulate a *DRAM caches*, in gem5, which are primarily
modeled as page-based caches in the research community. But the gem5
simulator only supports a maximum of *128 bytes* as the size of the
cacheline. I've seen the previous mailing lists in search of the answer,
but found nothing that would help me.
What is the best solution regarding this issue??
Thank you in advance :-)
Varun
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Saivarun R
2018-02-07 07:32:31 UTC
Permalink
Hi Jason,

As you pointed out, I went through the dram_ctrl.cc file and spent some
time designing the implementation. I want to know if what I understood is
correct regarding the implementation or not.

Firstly, there is need of a block structure in dram_ctrl to hold the data.
Then a tag store array for tags. Most importantly, implementing the Master
port functionalities. Though I looked at your tutorials about the ports,
I'm unable to visualize the interactions possible in the current scenario.
I need help in this regard.

And thinking further, I have an idea of creating a wrapper class for the
cacheblks in gem5, which will arrange the cacheblks (of cacheline size 64
bytes) to form a larger "cache-line" (arrange 16 cacheblks to form a 1KB
cache-line size) in the cache. Is it possible to realize different
cacheline sizes with this idea.

Regards
Varun
Jason Lowe-Power
2018-02-08 17:09:09 UTC
Permalink
Hi Varun,

Some comments inline below.
Post by Saivarun R
Hi Jason,
As you pointed out, I went through the dram_ctrl.cc file and spent some
time designing the implementation. I want to know if what I understood is
correct regarding the implementation or not.
Firstly, there is need of a block structure in dram_ctrl to hold the data.
Then a tag store array for tags.
You will need tags in your cache, but the DRAM controller does not need
tags.
Post by Saivarun R
Most importantly, implementing the Master port functionalities. Though I
looked at your tutorials about the ports, I'm unable to visualize the
interactions possible in the current scenario. I need help in this regard.
See
http://learning.gem5.org/book/part2/memoryobject.html#gem5-master-and-slave-ports.
Beyond those pictures and the example code, I'm not sure I can give you
more guidance.
Post by Saivarun R
And thinking further, I have an idea of creating a wrapper class for the
cacheblks in gem5, which will arrange the cacheblks (of cacheline size 64
bytes) to form a larger "cache-line" (arrange 16 cacheblks to form a 1KB
cache-line size) in the cache. Is it possible to realize different
cacheline sizes with this idea.
Sure. Search for sub-blocked caches. This is what you would be implementing.
Post by Saivarun R
Regards
Varun
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Saivarun R
2018-02-09 03:49:33 UTC
Permalink
Hi Jason,

Thank you for the your help. I will work on that.

Thank you
Varun
Post by Jason Lowe-Power
Hi Varun,
Some comments inline below.
Post by Saivarun R
Hi Jason,
As you pointed out, I went through the dram_ctrl.cc file and spent some
time designing the implementation. I want to know if what I understood is
correct regarding the implementation or not.
Firstly, there is need of a block structure in dram_ctrl to hold the
data. Then a tag store array for tags.
You will need tags in your cache, but the DRAM controller does not need
tags.
Post by Saivarun R
Most importantly, implementing the Master port functionalities. Though I
looked at your tutorials about the ports, I'm unable to visualize the
interactions possible in the current scenario. I need help in this regard.
See http://learning.gem5.org/book/part2/memoryobject.html#
gem5-master-and-slave-ports. Beyond those pictures and the example code,
I'm not sure I can give you more guidance.
Post by Saivarun R
And thinking further, I have an idea of creating a wrapper class for the
cacheblks in gem5, which will arrange the cacheblks (of cacheline size 64
bytes) to form a larger "cache-line" (arrange 16 cacheblks to form a 1KB
cache-line size) in the cache. Is it possible to realize different
cacheline sizes with this idea.
Sure. Search for sub-blocked caches. This is what you would be
implementing.
Post by Saivarun R
Regards
Varun
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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