[gem5-users] Mapping accelerator in memory with DerivO3CPU

[João Miguel Morgado Pereira Vieira]

Hi guys,

I am new using gem5, and I am trying to use the simulator to measure the performance of an accelerator. While going through the documentation to learn how to map an accelerator in memory, I discovered powerjg's GitHub repository (https://github.com/powerjg/gem5/blob/devel/accel/src/accel/daxpy.cc <https://github.com/powerjg/gem5/blob/devel/accel/src/accel/daxpy.cc>), which helped me a lot (if you are reading this e-mail, thank you). However, to map the accelerator in memory, a crossbar has to be placed between the CPU data port and the L1 data cache, which apparently is not supported by the DerivO3CPU model (https://www.mail-archive.com/gem5-***@gem5.org/msg14005.html <https://www.mail-archive.com/gem5-***@gem5.org/msg14005.html>). The scheme seems something like this:



I really need to put this to work with the DerivO3CPU model, for performance comparison reasons.

If someone has any suggestion how to bypass this problem, I would be extremely grateful.

Thank you in advance,
Joao Vieira