g***@bsc.es
2018-10-01 08:09:09 UTC
Hello,
I want to study the performance impact of TLB miss ratio. I am using gem5 in
FS mode for x86. For my research I need a 2-level TLB. I am looking in the
files of the configuration of TLB but i can not find implementation for 2-
level TLB in x86. If someone knows about 2-level TLBs or has already
implemented one in gem5 please let me know!
I want to study the performance impact of TLB miss ratio. I am using gem5 in
FS mode for x86. For my research I need a 2-level TLB. I am looking in the
files of the configuration of TLB but i can not find implementation for 2-
level TLB in x86. If someone knows about 2-level TLBs or has already
implemented one in gem5 please let me know!