Discussion:
Adding CommMonitor between CPU and L1d-cache
(too old to reply)
Aditya Deshpande
2014-01-30 22:44:39 UTC
Permalink
Hi,
I want to add the CommMonitor between CPU and L1d-cache in SE mode to trace
all the memory operation requests in the system. I am running in x-86 SE
mode

I added following lines in the /src/cpu/BaseCPU.py file

system.monitor3 = CommMonitor(trace_file="CT_mon3.txt")
MasterPort("Data Port") = system.monitor3.master
system.monitor3.slave = dcache_port

and commented the following line
dcache_port = MasterPort("Data Port")

The code executes but the trace file does not get generated. The
CommMonitor3 also does not get recorded in config.ini.

How to generate this trace? Any alternate ideas that I can try.

Regards,
Aditya
Andreas Hansson
2014-01-30 23:44:39 UTC
Permalink
Hi Aditya,

The monitor is a sort of “extension cord”, so you have to modify the point where two ports are connected, e.g.

cpu.dcache_port = cache.cpu_side

would instead become:

cpu.monitor = CommMonitor(trace_file = “cpu.ptrc”) # note that the trace is not an ASCII text file, but a binary protobuf file
cpu.dcache_port = cpu.monitor.slave
cpu.monitor.master = cache.cpu_side

I hope that helps.

Andreas

From: Aditya Deshpande <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Thursday, 30 January 2014 22:44
To: "gem5-***@gem5.org<mailto:gem5-***@gem5.org>" <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: [gem5-users] Adding CommMonitor between CPU and L1d-cache

Hi,
I want to add the CommMonitor between CPU and L1d-cache in SE mode to trace all the memory operation requests in the system. I am running in x-86 SE mode

I added following lines in the /src/cpu/BaseCPU.py file

system.monitor3 = CommMonitor(trace_file="CT_mon3.txt")
MasterPort("Data Port") = system.monitor3.master
system.monitor3.slave = dcache_port

and commented the following line
dcache_port = MasterPort("Data Port")

The code executes but the trace file does not get generated. The CommMonitor3 also does not get recorded in config.ini.

How to generate this trace? Any alternate ideas that I can try.

Regards,
Aditya

-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Ahmad Hassan
2014-02-10 15:17:03 UTC
Permalink
Hi Andreas,

I successfully managed to attach CommMonitor between CPU and L1 and got the
trace as per your code suggestion:
cpu.L1MONITOR = CommMonitor(trace_file = "cpu.ptrc")
cpu.dcache_port = cpu.L1MONITOR.slave
cpu.L1MONITOR.master = cache.cpu_side

But I do not see any read and write packets. I only see pkt->cmdString of
type 'ReadResp' or 'WriteResp' in commonitor. In other words, I only see
the response packets from L1 to CPU but no traffic from CPU to L1. My
config looks like below:

[image: Inline images 1]

Any clues please?

Thanks,

Ahmad
Post by Andreas Hansson
Hi Aditya,
The monitor is a sort of "extension cord", so you have to modify the
point where two ports are connected, e.g.
cpu.dcache_port = cache.cpu_side
cpu.monitor = CommMonitor(trace_file = "cpu.ptrc") # note that the trace
is not an ASCII text file, but a binary protobuf file
cpu.dcache_port = cpu.monitor.slave
cpu.monitor.master = cache.cpu_side
I hope that helps.
Andreas
Date: Thursday, 30 January 2014 22:44
Subject: [gem5-users] Adding CommMonitor between CPU and L1d-cache
Hi,
I want to add the CommMonitor between CPU and L1d-cache in SE mode to
trace all the memory operation requests in the system. I am running in x-86
SE mode
I added following lines in the /src/cpu/BaseCPU.py file
system.monitor3 = CommMonitor(trace_file="CT_mon3.txt")
MasterPort("Data Port") = system.monitor3.master
system.monitor3.slave = dcache_port
and commented the following line
dcache_port = MasterPort("Data Port")
The code executes but the trace file does not get generated. The
CommMonitor3 also does not get recorded in config.ini.
How to generate this trace? Any alternate ideas that I can try.
Regards,
Aditya
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Andreas Hansson
2014-02-10 16:53:53 UTC
Permalink
Hi Ahmad,

I’m not sure what print-outs you are referring to. Are you printing the trace after capture?

The monitor takes special care to store the fields of the packet before forwarding it. If you have added your own print statements, then the packet is most likely changed already, explaining why you see only responses.

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Monday, 10 February 2014 15:17
To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Adding CommMonitor between CPU and L1d-cache

Hi Andreas,

I successfully managed to attach CommMonitor between CPU and L1 and got the trace as per your code suggestion:
cpu.L1MONITOR = CommMonitor(trace_file = “cpu.ptrc”)
cpu.dcache_port = cpu.L1MONITOR.slave
cpu.L1MONITOR.master = cache.cpu_side

But I do not see any read and write packets. I only see pkt->cmdString of type 'ReadResp' or 'WriteResp' in commonitor. In other words, I only see the response packets from L1 to CPU but no traffic from CPU to L1. My config looks like below:

[cid:ii_1441c5e34f728e1f]

Any clues please?

Thanks,

Ahmad


On 30 January 2014 23:44, Andreas Hansson <***@arm.com<mailto:***@arm.com>> wrote:
Hi Aditya,

The monitor is a sort of “extension cord”, so you have to modify the point where two ports are connected, e.g.

cpu.dcache_port = cache.cpu_side

would instead become:

cpu.monitor = CommMonitor(trace_file = “cpu.ptrc”) # note that the trace is not an ASCII text file, but a binary protobuf file
cpu.dcache_port = cpu.monitor.slave
cpu.monitor.master = cache.cpu_side

I hope that helps.

Andreas

From: Aditya Deshpande <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Thursday, 30 January 2014 22:44
To: "gem5-***@gem5.org<mailto:gem5-***@gem5.org>" <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: [gem5-users] Adding CommMonitor between CPU and L1d-cache

Hi,
I want to add the CommMonitor between CPU and L1d-cache in SE mode to trace all the memory operation requests in the system. I am running in x-86 SE mode

I added following lines in the /src/cpu/BaseCPU.py file

system.monitor3 = CommMonitor(trace_file="CT_mon3.txt")
MasterPort("Data Port") = system.monitor3.master
system.monitor3.slave = dcache_port

and commented the following line
dcache_port = MasterPort("Data Port")

The code executes but the trace file does not get generated. The CommMonitor3 also does not get recorded in config.ini.

How to generate this trace? Any alternate ideas that I can try.

Regards,
Aditya

-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782

_______________________________________________
gem5-users mailing list
gem5-***@gem5.org<mailto:gem5-***@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Ahmad Hassan
2014-02-10 17:03:51 UTC
Permalink
Hi Andreas,

I didn't modify the packet. I just modified the following print statement
in recvTimingReq of CommMonitor

DPRINTF(CommMonitor, "Forwarded read request"); ==> DPRINTF(CommMonitor,
"Forwarded read request %s", pkt->cmdString());

I am running full system x86 simulation in detailed mode.

Thanks.

Ahmad
Post by Andreas Hansson
Hi Ahmad,
I'm not sure what print-outs you are referring to. Are you printing the
trace after capture?
The monitor takes special care to store the fields of the packet before
forwarding it. If you have added your own print statements, then the packet
is most likely changed already, explaining why you see only responses.
Andreas
Date: Monday, 10 February 2014 15:17
Subject: Re: [gem5-users] Adding CommMonitor between CPU and L1d-cache
Hi Andreas,
I successfully managed to attach CommMonitor between CPU and L1 and got
cpu.L1MONITOR = CommMonitor(trace_file = "cpu.ptrc")
cpu.dcache_port = cpu.L1MONITOR.slave
cpu.L1MONITOR.master = cache.cpu_side
But I do not see any read and write packets. I only see pkt->cmdString
of type 'ReadResp' or 'WriteResp' in commonitor. In other words, I only see
the response packets from L1 to CPU but no traffic from CPU to L1. My
[image: Inline images 1]
Any clues please?
Thanks,
Ahmad
Post by Andreas Hansson
Hi Aditya,
The monitor is a sort of "extension cord", so you have to modify the
point where two ports are connected, e.g.
cpu.dcache_port = cache.cpu_side
cpu.monitor = CommMonitor(trace_file = "cpu.ptrc") # note that the
trace is not an ASCII text file, but a binary protobuf file
cpu.dcache_port = cpu.monitor.slave
cpu.monitor.master = cache.cpu_side
I hope that helps.
Andreas
Date: Thursday, 30 January 2014 22:44
Subject: [gem5-users] Adding CommMonitor between CPU and L1d-cache
Hi,
I want to add the CommMonitor between CPU and L1d-cache in SE mode to
trace all the memory operation requests in the system. I am running in x-86
SE mode
I added following lines in the /src/cpu/BaseCPU.py file
system.monitor3 = CommMonitor(trace_file="CT_mon3.txt")
MasterPort("Data Port") = system.monitor3.master
system.monitor3.slave = dcache_port
and commented the following line
dcache_port = MasterPort("Data Port")
The code executes but the trace file does not get generated. The
CommMonitor3 also does not get recorded in config.ini.
How to generate this trace? Any alternate ideas that I can try.
Regards,
Aditya
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Andreas Hansson
2014-02-10 17:14:20 UTC
Permalink
Hi Ahmad,

At that point the packet has already been passed to the next module, and the command is thus changed.

The trace should be fine.

Let me know how it goes.

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Monday, 10 February 2014 17:03
To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Adding CommMonitor between CPU and L1d-cache

Hi Andreas,

I didn't modify the packet. I just modified the following print statement in recvTimingReq of CommMonitor

DPRINTF(CommMonitor, "Forwarded read request"); ==> DPRINTF(CommMonitor, "Forwarded read request %s", pkt->cmdString());

I am running full system x86 simulation in detailed mode.

Thanks.

Ahmad



On 10 February 2014 16:53, Andreas Hansson <***@arm.com<mailto:***@arm.com>> wrote:
Hi Ahmad,

I’m not sure what print-outs you are referring to. Are you printing the trace after capture?

The monitor takes special care to store the fields of the packet before forwarding it. If you have added your own print statements, then the packet is most likely changed already, explaining why you see only responses.

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>

Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Monday, 10 February 2014 15:17

To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Adding CommMonitor between CPU and L1d-cache

Hi Andreas,

I successfully managed to attach CommMonitor between CPU and L1 and got the trace as per your code suggestion:
cpu.L1MONITOR = CommMonitor(trace_file = “cpu.ptrc”)
cpu.dcache_port = cpu.L1MONITOR.slave
cpu.L1MONITOR.master = cache.cpu_side

But I do not see any read and write packets. I only see pkt->cmdString of type 'ReadResp' or 'WriteResp' in commonitor. In other words, I only see the response packets from L1 to CPU but no traffic from CPU to L1. My config looks like below:

[cid:ii_1441c5e34f728e1f]

Any clues please?

Thanks,

Ahmad


On 30 January 2014 23:44, Andreas Hansson <***@arm.com<mailto:***@arm.com>> wrote:
Hi Aditya,

The monitor is a sort of “extension cord”, so you have to modify the point where two ports are connected, e.g.

cpu.dcache_port = cache.cpu_side

would instead become:

cpu.monitor = CommMonitor(trace_file = “cpu.ptrc”) # note that the trace is not an ASCII text file, but a binary protobuf file
cpu.dcache_port = cpu.monitor.slave
cpu.monitor.master = cache.cpu_side

I hope that helps.

Andreas

From: Aditya Deshpande <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Thursday, 30 January 2014 22:44
To: "gem5-***@gem5.org<mailto:gem5-***@gem5.org>" <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: [gem5-users] Adding CommMonitor between CPU and L1d-cache

Hi,
I want to add the CommMonitor between CPU and L1d-cache in SE mode to trace all the memory operation requests in the system. I am running in x-86 SE mode

I added following lines in the /src/cpu/BaseCPU.py file

system.monitor3 = CommMonitor(trace_file="CT_mon3.txt")
MasterPort("Data Port") = system.monitor3.master
system.monitor3.slave = dcache_port

and commented the following line
dcache_port = MasterPort("Data Port")

The code executes but the trace file does not get generated. The CommMonitor3 also does not get recorded in config.ini.

How to generate this trace? Any alternate ideas that I can try.

Regards,
Aditya

-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782

_______________________________________________
gem5-users mailing list
gem5-***@gem5.org<mailto:gem5-***@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782

_______________________________________________
gem5-users mailing list
gem5-***@gem5.org<mailto:gem5-***@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Ahmad Hassan
2014-02-10 20:23:47 UTC
Permalink
Hi Andreas,

Great Thanks. It works perfectly fine and I can see all the read/write
requests. Is it possible to track each individual READ request through some
ID from CPU until it is served from the final destination e.g. DRAM, L2,
L1? I observe that the packets and request objects do not remain same from
CPU until the final destination DRAM/L2/L1? Also the physical and virtual
addresses change when packet travels from cpu->L1->L2->DRAM as well in X86
system.

Thanks.

Best Regards, Ahmad
Post by Andreas Hansson
Hi Ahmad,
At that point the packet has already been passed to the next module, and
the command is thus changed.
The trace should be fine.
Let me know how it goes.
Andreas
Date: Monday, 10 February 2014 17:03
Subject: Re: [gem5-users] Adding CommMonitor between CPU and L1d-cache
Hi Andreas,
I didn't modify the packet. I just modified the following print
statement in recvTimingReq of CommMonitor
DPRINTF(CommMonitor, "Forwarded read request");
==> DPRINTF(CommMonitor, "Forwarded read request %s", pkt->cmdString());
I am running full system x86 simulation in detailed mode.
Thanks.
Ahmad
Post by Andreas Hansson
Hi Ahmad,
I'm not sure what print-outs you are referring to. Are you printing the
trace after capture?
The monitor takes special care to store the fields of the packet before
forwarding it. If you have added your own print statements, then the packet
is most likely changed already, explaining why you see only responses.
Andreas
Date: Monday, 10 February 2014 15:17
Subject: Re: [gem5-users] Adding CommMonitor between CPU and L1d-cache
Hi Andreas,
I successfully managed to attach CommMonitor between CPU and L1 and got
cpu.L1MONITOR = CommMonitor(trace_file = "cpu.ptrc")
cpu.dcache_port = cpu.L1MONITOR.slave
cpu.L1MONITOR.master = cache.cpu_side
But I do not see any read and write packets. I only see pkt->cmdString
of type 'ReadResp' or 'WriteResp' in commonitor. In other words, I only see
the response packets from L1 to CPU but no traffic from CPU to L1. My
[image: Inline images 1]
Any clues please?
Thanks,
Ahmad
Post by Andreas Hansson
Hi Aditya,
The monitor is a sort of "extension cord", so you have to modify the
point where two ports are connected, e.g.
cpu.dcache_port = cache.cpu_side
cpu.monitor = CommMonitor(trace_file = "cpu.ptrc") # note that the
trace is not an ASCII text file, but a binary protobuf file
cpu.dcache_port = cpu.monitor.slave
cpu.monitor.master = cache.cpu_side
I hope that helps.
Andreas
Date: Thursday, 30 January 2014 22:44
Subject: [gem5-users] Adding CommMonitor between CPU and L1d-cache
Hi,
I want to add the CommMonitor between CPU and L1d-cache in SE mode to
trace all the memory operation requests in the system. I am running in x-86
SE mode
I added following lines in the /src/cpu/BaseCPU.py file
system.monitor3 = CommMonitor(trace_file="CT_mon3.txt")
MasterPort("Data Port") = system.monitor3.master
system.monitor3.slave = dcache_port
and commented the following line
dcache_port = MasterPort("Data Port")
The code executes but the trace file does not get generated. The
CommMonitor3 also does not get recorded in config.ini.
How to generate this trace? Any alternate ideas that I can try.
Regards,
Aditya
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1
9NJ, Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Andreas Hansson
2014-02-10 22:40:36 UTC
Permalink
Hi Ahmad,

Good to hear it works. The packets will indeed be different, as they are created by the caches etc. You should, however, see the same request throughout the memory system.

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Monday, February 10, 2014 at 8:23 PM
To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Adding CommMonitor between CPU and L1d-cache

Hi Andreas,

Great Thanks. It works perfectly fine and I can see all the read/write requests. Is it possible to track each individual READ request through some ID from CPU until it is served from the final destination e.g. DRAM, L2, L1? I observe that the packets and request objects do not remain same from CPU until the final destination DRAM/L2/L1? Also the physical and virtual addresses change when packet travels from cpu->L1->L2->DRAM as well in X86 system.

Thanks.

Best Regards, Ahmad


On 10 February 2014 17:14, Andreas Hansson <***@arm.com<mailto:***@arm.com>> wrote:
Hi Ahmad,

At that point the packet has already been passed to the next module, and the command is thus changed.

The trace should be fine.

Let me know how it goes.

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Monday, 10 February 2014 17:03

To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Adding CommMonitor between CPU and L1d-cache

Hi Andreas,

I didn't modify the packet. I just modified the following print statement in recvTimingReq of CommMonitor

DPRINTF(CommMonitor, "Forwarded read request"); ==> DPRINTF(CommMonitor, "Forwarded read request %s", pkt->cmdString());

I am running full system x86 simulation in detailed mode.

Thanks.

Ahmad



On 10 February 2014 16:53, Andreas Hansson <***@arm.com<mailto:***@arm.com>> wrote:
Hi Ahmad,

I’m not sure what print-outs you are referring to. Are you printing the trace after capture?

The monitor takes special care to store the fields of the packet before forwarding it. If you have added your own print statements, then the packet is most likely changed already, explaining why you see only responses.

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>

Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Monday, 10 February 2014 15:17

To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Adding CommMonitor between CPU and L1d-cache

Hi Andreas,

I successfully managed to attach CommMonitor between CPU and L1 and got the trace as per your code suggestion:
cpu.L1MONITOR = CommMonitor(trace_file = “cpu.ptrc”)
cpu.dcache_port = cpu.L1MONITOR.slave
cpu.L1MONITOR.master = cache.cpu_side

But I do not see any read and write packets. I only see pkt->cmdString of type 'ReadResp' or 'WriteResp' in commonitor. In other words, I only see the response packets from L1 to CPU but no traffic from CPU to L1. My config looks like below:

[cid:ii_1441c5e34f728e1f]

Any clues please?

Thanks,

Ahmad


On 30 January 2014 23:44, Andreas Hansson <***@arm.com<mailto:***@arm.com>> wrote:
Hi Aditya,

The monitor is a sort of “extension cord”, so you have to modify the point where two ports are connected, e.g.

cpu.dcache_port = cache.cpu_side

would instead become:

cpu.monitor = CommMonitor(trace_file = “cpu.ptrc”) # note that the trace is not an ASCII text file, but a binary protobuf file
cpu.dcache_port = cpu.monitor.slave
cpu.monitor.master = cache.cpu_side

I hope that helps.

Andreas

From: Aditya Deshpande <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Thursday, 30 January 2014 22:44
To: "gem5-***@gem5.org<mailto:gem5-***@gem5.org>" <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: [gem5-users] Adding CommMonitor between CPU and L1d-cache

Hi,
I want to add the CommMonitor between CPU and L1d-cache in SE mode to trace all the memory operation requests in the system. I am running in x-86 SE mode

I added following lines in the /src/cpu/BaseCPU.py file

system.monitor3 = CommMonitor(trace_file="CT_mon3.txt")
MasterPort("Data Port") = system.monitor3.master
system.monitor3.slave = dcache_port

and commented the following line
dcache_port = MasterPort("Data Port")

The code executes but the trace file does not get generated. The CommMonitor3 also does not get recorded in config.ini.

How to generate this trace? Any alternate ideas that I can try.

Regards,
Aditya

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ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782

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-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Aditya Deshpande
2014-01-31 21:33:52 UTC
Permalink
Andreas,

I understand how to add CommMonitor. I was able to trace L2 cache accesses
using CommMonitor. In that case, I was adding commMonitor in
config/common/CacheConfig.py
I was able to run the simulation and get the trace. The commMonitor
connections also showed in config.ini file

Now given that interface between CPU and L1 cache is set in
/src/cpu/BaseCPU.py In that file when I add commMonitor between cpu
dcache_port and L1dcache cpu_side nothing happens. The simulation completes
but I don't see a trace file for this commMonitor, nor do I see any info
regarding this commMonitor in config.ini file.

when adding commMonitor in /src/cpu/BaseCPU.py do I need to rebuilt the
system by running scons command before execution?

Regards,
Aditya
Ahmad Hassan
2014-02-11 11:36:26 UTC
Permalink
Hi Aditiya,

[Putting on the list so other people can benefit too]

It is not required to add any 'include' header in src/cpu/BaseCPU.py. The
reason you are getting this error is because scon build system hasn't
compiled the CommMonitor code. You should see this as a WARNING during scon
build process that protobuf iss missing. SCON checks for google protocol
buffer on your system and if scon doesn't find it then 'have_protobuf' is
set to '0' and CommMonitor is not included in the build repo. You have to
install google protobuf then set PROTOC environment variable to the
installed dir.

Then you need to rebuild gem5 as:

scons -j6 build/X86/gem5.opt

This time scon will build all the CommMonitor classes and you won't see any
errors like '"NameError: global name 'CommMonitor' is not defined"'

Caution: I set the PROTOC environ variable in the shell but still scon
doesn't pick it up. One way of getting around this is to change SConstruct
and provide the protoc path as '/usr/bin/protoc' instead of reading from
environment variable:

('PROTOC', 'protoc tool', "/usr/bin/protoc"),

Hope this helps.

Best Regards, Ahmad
Post by Andreas Hansson
Ahmad,
Thanks for the info. I had tried adding in similar way. After adding these
lines, I need to recompile the code. During recompilation, it gives me an
error
"NameError: global name 'CommMonitor' is not defined"
Any pointers on how you got over this error. Did you add any header files
in src/cpu/BaseCPU.py
Regards,
Aditya
Post by Andreas Hansson
Hi Aditya,
Thank for the email. i added commmonitor between cpu and L1
in src/cpu/BaseCPU.py as follows
#self.dcache_port = dc.cpu_side
self.L1MONITOR = CommMonitor(trace_file="L1");
self.dcache_port = self.L1MONITOR.slave
self.L1MONITOR.master = dc.cpu_side
Good luck.
Best Regards, Ahmad
Ahmed,
If you want to add CommMonitor between l1 and L2 cache
In CacheConfig.py
Comment following lines
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
Add following lines
system.monitor2 = CommMonitor(trace_file="CT_mon2.txt")
system.monitor2.slave = system.tol2bus.master
system.l2.cpu_side = system.monitor2.master
system.l2.mem_side = system.membus.slave
The following lines basically changes the hierarchy from (l1-cache ->
tol2bus -> L2 Cache ->membus) to (l1cache -> tol2bus -> commMonitor
monitor2 -> l2cache -> membus)
I ran into same problem of CommMonitor being not found when i try to add
commMonitor between CPU and L1D-cache.
Did you try to add any CommMonitor there? Any ideas on how to do that.
Regards,
Aditya
HI Aditya,
How did you attach commonitor to L2 in config/common/CacheConfig.py. I
get import errors if I try to import 'from CommMonitor import *" in
CacheConfig.py
Please can you share the syntax of attaching L2 and L1 to commmonitor.
Thanks.
Post by Aditya Deshpande
Andreas,
I understand how to add CommMonitor. I was able to trace L2 cache
accesses using CommMonitor. In that case, I was adding commMonitor in
config/common/CacheConfig.py
I was able to run the simulation and get the trace. The commMonitor
connections also showed in config.ini file
Now given that interface between CPU and L1 cache is set in
/src/cpu/BaseCPU.py In that file when I add commMonitor between cpu
dcache_port and L1dcache cpu_side nothing happens. The simulation completes
but I don't see a trace file for this commMonitor, nor do I see any info
regarding this commMonitor in config.ini file.
when adding commMonitor in /src/cpu/BaseCPU.py do I need to rebuilt
the system by running scons command before execution?
Regards,
Aditya
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Andreas Hansson
2014-02-11 13:45:37 UTC
Permalink
Hi Ahmad,

Thanks for making this clear.

We decided a while back to not make protobuf and protoc a dependency, hence the adaptive build process. I had completely forgotten about this. Perhaps it would be time to reconsider.

I have ensured that the PROTOC variable is now passed on from the environment. I’ll push this patch in the next few days. If you have protoc in your path it should “just work” though. Are you suggesting it doesn’t?

Thanks,

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Tuesday, 11 February 2014 11:36
To: Aditya Deshpande <***@gmail.com<mailto:***@gmail.com>>, gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Adding CommMonitor between CPU and L1d-cache

Hi Aditiya,

[Putting on the list so other people can benefit too]

It is not required to add any 'include' header in src/cpu/BaseCPU.py. The reason you are getting this error is because scon build system hasn't compiled the CommMonitor code. You should see this as a WARNING during scon build process that protobuf iss missing. SCON checks for google protocol buffer on your system and if scon doesn't find it then 'have_protobuf' is set to '0' and CommMonitor is not included in the build repo. You have to install google protobuf then set PROTOC environment variable to the installed dir.

Then you need to rebuild gem5 as:

scons -j6 build/X86/gem5.opt

This time scon will build all the CommMonitor classes and you won't see any errors like '"NameError: global name 'CommMonitor' is not defined"'

Caution: I set the PROTOC environ variable in the shell but still scon doesn't pick it up. One way of getting around this is to change SConstruct and provide the protoc path as '/usr/bin/protoc' instead of reading from environment variable:

('PROTOC', 'protoc tool', "/usr/bin/protoc"),

Hope this helps.

Best Regards, Ahmad



On 11 February 2014 00:20, Aditya Deshpande <***@gmail.com<mailto:***@gmail.com>> wrote:
Ahmad,

Thanks for the info. I had tried adding in similar way. After adding these lines, I need to recompile the code. During recompilation, it gives me an error

"NameError: global name 'CommMonitor' is not defined"

Any pointers on how you got over this error. Did you add any header files in src/cpu/BaseCPU.py



Regards,
Aditya


On Mon, Feb 10, 2014 at 9:21 AM, Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>> wrote:
Hi Aditya,

Thank for the email. i added commmonitor between cpu and L1 in src/cpu/BaseCPU.py as follows

#self.dcache_port = dc.cpu_side
self.L1MONITOR = CommMonitor(trace_file="L1");
self.dcache_port = self.L1MONITOR.slave
self.L1MONITOR.master = dc.cpu_side

Good luck.

Best Regards, Ahmad


On 10 February 2014 17:03, Aditya Deshpande <***@gmail.com<mailto:***@gmail.com>> wrote:
Ahmed,

If you want to add CommMonitor between l1 and L2 cache

In CacheConfig.py

Comment following lines
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave

Add following lines
system.monitor2 = CommMonitor(trace_file="CT_mon2.txt")
system.monitor2.slave = system.tol2bus.master
system.l2.cpu_side = system.monitor2.master
system.l2.mem_side = system.membus.slave


The following lines basically changes the hierarchy from (l1-cache -> tol2bus -> L2 Cache ->membus) to (l1cache -> tol2bus -> commMonitor monitor2 -> l2cache -> membus)

I ran into same problem of CommMonitor being not found when i try to add commMonitor between CPU and L1D-cache.

Did you try to add any CommMonitor there? Any ideas on how to do that.


Regards,
Aditya


On Sun, Feb 9, 2014 at 1:38 AM, Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>> wrote:
HI Aditya,

How did you attach commonitor to L2 in config/common/CacheConfig.py. I get import errors if I try to import 'from CommMonitor import *" in CacheConfig.py

Please can you share the syntax of attaching L2 and L1 to commmonitor.

Thanks.




On 31 January 2014 21:33, Aditya Deshpande <***@gmail.com<mailto:***@gmail.com>> wrote:
Andreas,

I understand how to add CommMonitor. I was able to trace L2 cache accesses using CommMonitor. In that case, I was adding commMonitor in config/common/CacheConfig.py
I was able to run the simulation and get the trace. The commMonitor connections also showed in config.ini file

Now given that interface between CPU and L1 cache is set in /src/cpu/BaseCPU.py In that file when I add commMonitor between cpu dcache_port and L1dcache cpu_side nothing happens. The simulation completes but I don't see a trace file for this commMonitor, nor do I see any info regarding this commMonitor in config.ini file.

when adding commMonitor in /src/cpu/BaseCPU.py do I need to rebuilt the system by running scons command before execution?

Regards,
Aditya

_______________________________________________
gem5-users mailing list
gem5-***@gem5.org<mailto:gem5-***@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users






-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Aditya Deshpande
2014-02-11 16:50:07 UTC
Permalink
Ahmad / Andreas,

I had installed protobuf before. Still get the error when I add CommMonitor
in /src/cpu/BaseCPU.py file. Enclosed is the log for compilation and
execution dump.

oneloa 785% scons -j 8 build/X86_MESI_Two_Level/gem5.opt
scons: Reading SConscript files ...
Checking for leading underscore in global variables...(cached) no
Checking for C header file Python.h... (cached) yes
Checking for C library pthread... (cached) yes
Checking for C library dl... (cached) yes
Checking for C library util... (cached) yes
Checking for C library m... (cached) yes
Checking for C library python2.6... (cached) yes
Checking for accept(0,0,0) in C++ library None... (cached) yes
Checking for zlibVersion() in C++ library z... (cached) yes
Checking for GOOGLE_PROTOBUF_VERIFY_VERSION in C++ library protobuf...
(cached) yes
Checking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached) no
Checking for clock_nanosleep(0,0,NULL,NULL) in C library rt... (cached) yes
Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library None...
(cached) yes
Checking for C library tcmalloc... (cached) yes
Checking for C header file fenv.h... (cached) yes
Checking for C header file linux/kvm.h... (cached) yes
Checking size of struct kvm_xsave ... (cached) yes
Checking for member exclude_host in struct perf_event_attr...(cached) yes
Reading SConsopts
Building in /nfs/div1/adeshpan/arch/gem5/build/X86_MESI_Two_Level
Using saved variables file
/nfs/div1/adeshpan/arch/gem5/build/variables/X86_MESI_Two_Level
scons: done reading SConscript files.

scons: warning: Support for pre-2.7.0 Python version (2.6.6) is deprecated.
If this will cause hardship, contact ***@scons.tigris.org.
File "/usr/ucb/scons", line 192, in <module>
scons: Building targets ...
[SO PARAM] BaseCPU -> X86_MESI_Two_Level/params/BaseCPU.hh
[ SO SWIG] BaseCPU -> X86_MESI_Two_Level/python/m5/internal/param_BaseCPU.i
[EMBED PY] X86_MESI_Two_Level/cpu/BaseCPU.py -> .cc
[ CXX]
X86_MESI_Two_Level/python/m5/internal/param_BaseSimpleCPU_wrap.cc -> .o
[ CXX]
X86_MESI_Two_Level/python/m5/internal/param_TimingSimpleCPU_wrap.cc -> .o
[ CXX]
X86_MESI_Two_Level/python/m5/internal/param_DummyChecker_wrap.cc -> .o
[ CXX] X86_MESI_Two_Level/python/m5/internal/param_CheckerCPU_wrap.cc
-> .o
[ CXX] X86_MESI_Two_Level/python/m5/internal/param_O3Checker_wrap.cc
-> .o
[ CXX]
X86_MESI_Two_Level/python/m5/internal/param_AtomicSimpleCPU_wrap.cc -> .o
[ CXX] X86_MESI_Two_Level/python/m5/internal/param_BaseCPU_wrap.cc ->
.o
[ CXX] X86_MESI_Two_Level/python/m5/internal/param_BaseKvmCPU_wrap.cc
-> .o
[ CXX] X86_MESI_Two_Level/python/m5/internal/param_DerivO3CPU_wrap.cc
-> .o
[ CXX] X86_MESI_Two_Level/python/m5/internal/param_X86KvmCPU_wrap.cc
-> .o
scons: `build/X86_MESI_Two_Level/gem5.opt' is up to date.
scons: done building targets.

oneloa 786% ./build/X86_MESI_Two_Level/gem5.opt -v -d
/nfs/data-nas1/adeshpan/gem5 --debug-start=0 --debug-file=comm1.txt.gz
--debug-flags=Cache,CommMonitor,CachePort,Flag1AD
--stats-file=comm1stats.txt configs/example/se.py --caches
--cpu-type=TimingSimpleCPU --num-cpus=1 --l2cache --cpu-clock=1GHz -c
tests/test-progs/hello/bin/x86/linux/hello
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Feb 11 2014 08:19:42
gem5 started Feb 11 2014 08:45:13
gem5 executing on oneloa.isi.edu
command line: ./build/X86_MESI_Two_Level/gem5.opt -v -d
/nfs/data-nas1/adeshpan/gem5 --debug-start=0 --debug-file=comm1.txt.gz
--debug-flags=Cache,CommMonitor,CachePort,Flag1AD
--stats-file=comm1stats.txt configs/example/se.py --caches
--cpu-type=TimingSimpleCPU --num-cpus=1 --l2cache --cpu-clock=1GHz -c
tests/test-progs/hello/bin/x86/linux/hello
Traceback (most recent call last):
File "<string>", line 1, in <module>
File "/nfs/div1/adeshpan/arch/gem5/src/python/m5/main.py", line 388, in
main
exec filecode in scope
File "configs/example/se.py", line 254, in <module>
CacheConfig.config_cache(options, system)
File "/nfs/div1/adeshpan/arch/gem5/configs/common/CacheConfig.py", line
93, in config_cache
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(), PageTableWalkerCache())
File "/nfs/div1/adeshpan/arch/gem5/src/cpu/BaseCPU.py", line 274, in
addPrivateSplitL1Caches
self.monitor3 = CommMonitor(trace_file ="CT_mon3.ptrc")
NameError: global name 'CommMonitor' is not defined



Anything else I can try? I tried adding the CommMonitor files in the
src/cpu folder, that also doesn't seem to work.



Regards,
Aditya
Post by Ahmad Hassan
Hi Aditiya,
[Putting on the list so other people can benefit too]
It is not required to add any 'include' header in src/cpu/BaseCPU.py.
The reason you are getting this error is because scon build system hasn't
compiled the CommMonitor code. You should see this as a WARNING during scon
build process that protobuf iss missing. SCON checks for google protocol
buffer on your system and if scon doesn't find it then 'have_protobuf' is
set to '0' and CommMonitor is not included in the build repo. You have to
install google protobuf then set PROTOC environment variable to the
installed dir.
scons -j6 build/X86/gem5.opt
This time scon will build all the CommMonitor classes and you won't see
any errors like '"NameError: global name 'CommMonitor' is not defined"'
Caution: I set the PROTOC environ variable in the shell but still scon
doesn't pick it up. One way of getting around this is to change
SConstruct and provide the protoc path as '/usr/bin/protoc' instead of
('PROTOC', 'protoc tool', "/usr/bin/protoc"),
Hope this helps.
Best Regards, Ahmad
Post by Andreas Hansson
Ahmad,
Thanks for the info. I had tried adding in similar way. After adding
these lines, I need to recompile the code. During recompilation, it gives
me an error
"NameError: global name 'CommMonitor' is not defined"
Any pointers on how you got over this error. Did you add any header files
in src/cpu/BaseCPU.py
Regards,
Aditya
Post by Andreas Hansson
Hi Aditya,
Thank for the email. i added commmonitor between cpu and L1
in src/cpu/BaseCPU.py as follows
#self.dcache_port = dc.cpu_side
self.L1MONITOR = CommMonitor(trace_file="L1");
self.dcache_port = self.L1MONITOR.slave
self.L1MONITOR.master = dc.cpu_side
Good luck.
Best Regards, Ahmad
Ahmed,
If you want to add CommMonitor between l1 and L2 cache
In CacheConfig.py
Comment following lines
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
Add following lines
system.monitor2 = CommMonitor(trace_file="CT_mon2.txt")
system.monitor2.slave = system.tol2bus.master
system.l2.cpu_side = system.monitor2.master
system.l2.mem_side = system.membus.slave
The following lines basically changes the hierarchy from (l1-cache ->
tol2bus -> L2 Cache ->membus) to (l1cache -> tol2bus -> commMonitor
monitor2 -> l2cache -> membus)
I ran into same problem of CommMonitor being not found when i try to
add commMonitor between CPU and L1D-cache.
Did you try to add any CommMonitor there? Any ideas on how to do that.
Regards,
Aditya
HI Aditya,
How did you attach commonitor to L2 in config/common/CacheConfig.py.
I get import errors if I try to import 'from CommMonitor import *" in
CacheConfig.py
Please can you share the syntax of attaching L2 and L1 to commmonitor.
Thanks.
Post by Aditya Deshpande
Andreas,
I understand how to add CommMonitor. I was able to trace L2 cache
accesses using CommMonitor. In that case, I was adding commMonitor in
config/common/CacheConfig.py
I was able to run the simulation and get the trace. The commMonitor
connections also showed in config.ini file
Now given that interface between CPU and L1 cache is set in
/src/cpu/BaseCPU.py In that file when I add commMonitor between cpu
dcache_port and L1dcache cpu_side nothing happens. The simulation completes
but I don't see a trace file for this commMonitor, nor do I see any info
regarding this commMonitor in config.ini file.
when adding commMonitor in /src/cpu/BaseCPU.py do I need to rebuilt
the system by running scons command before execution?
Regards,
Aditya
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Ahmad Hassan
2014-02-11 20:10:49 UTC
Permalink
Hi Andreas,

Yes you are right, If 'protoc' is in the path then SCONS picks it up
automatically.

@Aditya:
You need to add 'from CommMonitor import *' in src/cpu/BaseCPU.py to get
CommMonitor module there. If that doesn't fix your problem then please can
you verify if 'build/X86/config/have_protobuf.hh' shows '#define
HAVE_PROTOBUF 1'

Best Regards, Ahmad
Post by Aditya Deshpande
Ahmad / Andreas,
I had installed protobuf before. Still get the error when I add
CommMonitor in /src/cpu/BaseCPU.py file. Enclosed is the log for
compilation and execution dump.
oneloa 785% scons -j 8 build/X86_MESI_Two_Level/gem5.opt
scons: Reading SConscript files ...
Checking for leading underscore in global variables...(cached) no
Checking for C header file Python.h... (cached) yes
Checking for C library pthread... (cached) yes
Checking for C library dl... (cached) yes
Checking for C library util... (cached) yes
Checking for C library m... (cached) yes
Checking for C library python2.6... (cached) yes
Checking for accept(0,0,0) in C++ library None... (cached) yes
Checking for zlibVersion() in C++ library z... (cached) yes
Checking for GOOGLE_PROTOBUF_VERIFY_VERSION in C++ library protobuf...
(cached) yes
Checking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached) no
Checking for clock_nanosleep(0,0,NULL,NULL) in C library rt... (cached) yes
Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library
None... (cached) yes
Checking for C library tcmalloc... (cached) yes
Checking for C header file fenv.h... (cached) yes
Checking for C header file linux/kvm.h... (cached) yes
Checking size of struct kvm_xsave ... (cached) yes
Checking for member exclude_host in struct perf_event_attr...(cached) yes
Reading SConsopts
Building in /nfs/div1/adeshpan/arch/gem5/build/X86_MESI_Two_Level
Using saved variables file
/nfs/div1/adeshpan/arch/gem5/build/variables/X86_MESI_Two_Level
scons: done reading SConscript files.
scons: warning: Support for pre-2.7.0 Python version (2.6.6) is deprecated.
File "/usr/ucb/scons", line 192, in <module>
scons: Building targets ...
[SO PARAM] BaseCPU -> X86_MESI_Two_Level/params/BaseCPU.hh
[ SO SWIG] BaseCPU ->
X86_MESI_Two_Level/python/m5/internal/param_BaseCPU.i
[EMBED PY] X86_MESI_Two_Level/cpu/BaseCPU.py -> .cc
[ CXX]
X86_MESI_Two_Level/python/m5/internal/param_BaseSimpleCPU_wrap.cc -> .o
[ CXX]
X86_MESI_Two_Level/python/m5/internal/param_TimingSimpleCPU_wrap.cc -> .o
[ CXX]
X86_MESI_Two_Level/python/m5/internal/param_DummyChecker_wrap.cc -> .o
[ CXX] X86_MESI_Two_Level/python/m5/internal/param_CheckerCPU_wrap.cc
-> .o
[ CXX] X86_MESI_Two_Level/python/m5/internal/param_O3Checker_wrap.cc
-> .o
[ CXX]
X86_MESI_Two_Level/python/m5/internal/param_AtomicSimpleCPU_wrap.cc -> .o
[ CXX] X86_MESI_Two_Level/python/m5/internal/param_BaseCPU_wrap.cc ->
.o
[ CXX] X86_MESI_Two_Level/python/m5/internal/param_BaseKvmCPU_wrap.cc
-> .o
[ CXX] X86_MESI_Two_Level/python/m5/internal/param_DerivO3CPU_wrap.cc
-> .o
[ CXX] X86_MESI_Two_Level/python/m5/internal/param_X86KvmCPU_wrap.cc
-> .o
scons: `build/X86_MESI_Two_Level/gem5.opt' is up to date.
scons: done building targets.
oneloa 786% ./build/X86_MESI_Two_Level/gem5.opt -v -d
/nfs/data-nas1/adeshpan/gem5 --debug-start=0 --debug-file=comm1.txt.gz
--debug-flags=Cache,CommMonitor,CachePort,Flag1AD
--stats-file=comm1stats.txt configs/example/se.py --caches
--cpu-type=TimingSimpleCPU --num-cpus=1 --l2cache --cpu-clock=1GHz -c
tests/test-progs/hello/bin/x86/linux/hello
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2014 08:19:42
gem5 started Feb 11 2014 08:45:13
gem5 executing on oneloa.isi.edu
command line: ./build/X86_MESI_Two_Level/gem5.opt -v -d
/nfs/data-nas1/adeshpan/gem5 --debug-start=0 --debug-file=comm1.txt.gz
--debug-flags=Cache,CommMonitor,CachePort,Flag1AD
--stats-file=comm1stats.txt configs/example/se.py --caches
--cpu-type=TimingSimpleCPU --num-cpus=1 --l2cache --cpu-clock=1GHz -c
tests/test-progs/hello/bin/x86/linux/hello
File "<string>", line 1, in <module>
File "/nfs/div1/adeshpan/arch/gem5/src/python/m5/main.py", line 388, in
main
exec filecode in scope
File "configs/example/se.py", line 254, in <module>
CacheConfig.config_cache(options, system)
File "/nfs/div1/adeshpan/arch/gem5/configs/common/CacheConfig.py", line
93, in config_cache
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(), PageTableWalkerCache())
File "/nfs/div1/adeshpan/arch/gem5/src/cpu/BaseCPU.py", line 274, in
addPrivateSplitL1Caches
self.monitor3 = CommMonitor(trace_file ="CT_mon3.ptrc")
NameError: global name 'CommMonitor' is not defined
Anything else I can try? I tried adding the CommMonitor files in the
src/cpu folder, that also doesn't seem to work.
Regards,
Aditya
Post by Ahmad Hassan
Hi Aditiya,
[Putting on the list so other people can benefit too]
It is not required to add any 'include' header in src/cpu/BaseCPU.py.
The reason you are getting this error is because scon build system hasn't
compiled the CommMonitor code. You should see this as a WARNING during scon
build process that protobuf iss missing. SCON checks for google protocol
buffer on your system and if scon doesn't find it then 'have_protobuf' is
set to '0' and CommMonitor is not included in the build repo. You have to
install google protobuf then set PROTOC environment variable to the
installed dir.
scons -j6 build/X86/gem5.opt
This time scon will build all the CommMonitor classes and you won't see
any errors like '"NameError: global name 'CommMonitor' is not defined"'
Caution: I set the PROTOC environ variable in the shell but still scon
doesn't pick it up. One way of getting around this is to change
SConstruct and provide the protoc path as '/usr/bin/protoc' instead of
('PROTOC', 'protoc tool', "/usr/bin/protoc"),
Hope this helps.
Best Regards, Ahmad
Post by Andreas Hansson
Ahmad,
Thanks for the info. I had tried adding in similar way. After adding
these lines, I need to recompile the code. During recompilation, it gives
me an error
"NameError: global name 'CommMonitor' is not defined"
Any pointers on how you got over this error. Did you add any header
files in src/cpu/BaseCPU.py
Regards,
Aditya
Post by Andreas Hansson
Hi Aditya,
Thank for the email. i added commmonitor between cpu and L1
in src/cpu/BaseCPU.py as follows
#self.dcache_port = dc.cpu_side
self.L1MONITOR = CommMonitor(trace_file="L1");
self.dcache_port = self.L1MONITOR.slave
self.L1MONITOR.master = dc.cpu_side
Good luck.
Best Regards, Ahmad
Ahmed,
If you want to add CommMonitor between l1 and L2 cache
In CacheConfig.py
Comment following lines
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
Add following lines
system.monitor2 = CommMonitor(trace_file="CT_mon2.txt")
system.monitor2.slave = system.tol2bus.master
system.l2.cpu_side = system.monitor2.master
system.l2.mem_side = system.membus.slave
The following lines basically changes the hierarchy from (l1-cache ->
tol2bus -> L2 Cache ->membus) to (l1cache -> tol2bus -> commMonitor
monitor2 -> l2cache -> membus)
I ran into same problem of CommMonitor being not found when i try to
add commMonitor between CPU and L1D-cache.
Did you try to add any CommMonitor there? Any ideas on how to do that.
Regards,
Aditya
HI Aditya,
How did you attach commonitor to L2 in config/common/CacheConfig.py.
I get import errors if I try to import 'from CommMonitor import *" in
CacheConfig.py
Please can you share the syntax of attaching L2 and L1 to
commmonitor.
Thanks.
On 31 January 2014 21:33, Aditya Deshpande <
Post by Aditya Deshpande
Andreas,
I understand how to add CommMonitor. I was able to trace L2 cache
accesses using CommMonitor. In that case, I was adding commMonitor in
config/common/CacheConfig.py
I was able to run the simulation and get the trace. The commMonitor
connections also showed in config.ini file
Now given that interface between CPU and L1 cache is set in
/src/cpu/BaseCPU.py In that file when I add commMonitor between cpu
dcache_port and L1dcache cpu_side nothing happens. The simulation completes
but I don't see a trace file for this commMonitor, nor do I see any info
regarding this commMonitor in config.ini file.
when adding commMonitor in /src/cpu/BaseCPU.py do I need to rebuilt
the system by running scons command before execution?
Regards,
Aditya
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Pei Luo
2014-02-15 02:42:30 UTC
Permalink
Post by Ahmad Hassan
Hi Andreas,
Yes you are right, If 'protoc' is in the path then SCONS picks it up
automatically.
Post by Ahmad Hassan
<at> Aditya: 
You need to add 'from CommMonitor import *' in src/cpu/BaseCPU.py to get
CommMonitor module there. If that doesn't fix your problem then please can
you verify if 'build/X86/config/have_protobuf.hh' shows '#define
HAVE_PROTOBUF 1'
Post by Ahmad Hassan
Best Regards, Ahmad
On 11 February 2014 16:50, Aditya Deshpande <adityamdeshpande <at>
Ahmad / Andreas,
I had installed protobuf before. Still get the error when I add
CommMonitor in /src/cpu/BaseCPU.py file.  Enclosed is the log for
compilation and execution dump.
Post by Ahmad Hassan
oneloa 785% scons -j 8 build/X86_MESI_Two_Level/gem5.optscons: Reading
SConscript files ...Checking for leading underscore in global
variables...(cached) noChecking for C header file Python.h... (cached) yes
Post by Ahmad Hassan
Checking for C library pthread... (cached) yesChecking for C library dl...
(cached) yesChecking for C library util... (cached) yesChecking for C
library m... (cached) yesChecking for C library python2.6... (cached) yes
Post by Ahmad Hassan
Checking for accept(0,0,0) in C++ library None... (cached) yesChecking for
zlibVersion() in C++ library z... (cached) yesChecking for
GOOGLE_PROTOBUF_VERIFY_VERSION in C++ library protobuf... (cached)
yesChecking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached) no
Post by Ahmad Hassan
Checking for clock_nanosleep(0,0,NULL,NULL) in C library rt... (cached)
yesChecking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library
None... (cached) yesChecking for C library tcmalloc... (cached) yes
Post by Ahmad Hassan
Checking for C header file fenv.h... (cached) yesChecking for C header
file linux/kvm.h... (cached) yesChecking size of struct kvm_xsave ...
(cached) yesChecking for member exclude_host in struct
perf_event_attr...(cached) yes
Post by Ahmad Hassan
Reading SConsoptsBuilding in
/nfs/div1/adeshpan/arch/gem5/build/X86_MESI_Two_LevelUsing saved variables
file /nfs/div1/adeshpan/arch/gem5/build/variables/X86_MESI_Two_Levelscons:
done reading SConscript files.scons: warning: Support for pre-2.7.0 Python
version (2.6.6) is deprecated.    If this will cause hardship, contact dev
<at> scons.tigris.org.File "/usr/ucb/scons", line 192, in <module>
Post by Ahmad Hassan
scons: Building targets ... [SO PARAM] BaseCPU ->
X86_MESI_Two_Level/params/BaseCPU.hh [ SO SWIG] BaseCPU ->
X86_MESI_Two_Level/python/m5/internal/param_BaseCPU.i [EMBED PY]
X86_MESI_Two_Level/cpu/BaseCPU.py -> .cc
Post by Ahmad Hassan
 [     CXX]
X86_MESI_Two_Level/python/m5/internal/param_BaseSimpleCPU_wrap.cc ->
.o [     CXX]
X86_MESI_Two_Level/python/m5/internal/param_TimingSimpleCPU_wrap.cc ->
.o [     CXX]
X86_MESI_Two_Level/python/m5/internal/param_DummyChecker_wrap.cc -> .o
Post by Ahmad Hassan
 [     CXX] X86_MESI_Two_Level/python/m5/internal/param_CheckerCPU_wrap.cc
-> .o [     CXX]
X86_MESI_Two_Level/python/m5/internal/param_O3Checker_wrap.cc -> .o [    
CXX] X86_MESI_Two_Level/python/m5/internal/param_AtomicSimpleCPU_wrap.cc -> .o
Post by Ahmad Hassan
 [     CXX] X86_MESI_Two_Level/python/m5/internal/param_BaseCPU_wrap.cc ->
.o [     CXX] X86_MESI_Two_Level/python/m5/internal/param_BaseKvmCPU_wrap.cc
-> .o [     CXX]
X86_MESI_Two_Level/python/m5/internal/param_DerivO3CPU_wrap.cc -> .o
Post by Ahmad Hassan
 [     CXX] X86_MESI_Two_Level/python/m5/internal/param_X86KvmCPU_wrap.cc
-> .oscons: `build/X86_MESI_Two_Level/gem5.opt' is up to date.scons: done
building targets.oneloa 786% ./build/X86_MESI_Two_Level/gem5.opt -v -d
/nfs/data-nas1/adeshpan/gem5 --debug-start=0 --debug-file=comm1.txt.gz
--debug-flags=Cache,CommMonitor,CachePort,Flag1AD
--stats-file=comm1stats.txt configs/example/se.py --caches
--cpu-type=TimingSimpleCPU --num-cpus=1 --l2cache --cpu-clock=1GHz -c
tests/test-progs/hello/bin/x86/linux/hello
Post by Ahmad Hassan
gem5 Simulator System.  http://gem5.orggem5 is copyrighted software; use
the --copyright option for details.gem5 compiled Feb 11 2014 08:19:42gem5
started Feb 11 2014 08:45:13
./build/X86_MESI_Two_Level/gem5.opt -v -d /nfs/data-nas1/adeshpan/gem5
--debug-start=0 --debug-file=comm1.txt.gz
--debug-flags=Cache,CommMonitor,CachePort,Flag1AD
--stats-file=comm1stats.txt configs/example/se.py --caches
--cpu-type=TimingSimpleCPU --num-cpus=1 --l2cache --cpu-clock=1GHz -c
tests/test-progs/hello/bin/x86/linux/hello
Post by Ahmad Hassan
Traceback (most recent call last):  File "<string>", line 1, in <module> 
File "/nfs/div1/adeshpan/arch/gem5/src/python/m5/main.py", line 388, in
main    exec filecode in scope
Post by Ahmad Hassan
  File "configs/example/se.py", line 254, in <module>   
CacheConfig.config_cache(options, system)  File
"/nfs/div1/adeshpan/arch/gem5/configs/common/CacheConfig.py", line 93, in
config_cache
Post by Ahmad Hassan
    system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(), PageTableWalkerCache())  File
"/nfs/div1/adeshpan/arch/gem5/src/cpu/BaseCPU.py", line 274, in
addPrivateSplitL1Caches    self.monitor3 = CommMonitor(trace_file
="CT_mon3.ptrc")
Post by Ahmad Hassan
NameError: global name 'CommMonitor' is not defined
Anything else I can try? I tried adding the CommMonitor files in the
src/cpu folder, that also doesn't seem to work.
Post by Ahmad Hassan
Regards,Aditya
On Tue, Feb 11, 2014 at 3:36 AM, Ahmad Hassan <ahmad.hassan <at>
Hi Aditiya,
[Putting on the list so other people can benefit too]
It is not required to add any 'include' header in 
src/cpu/BaseCPU.py. The reason you are getting this error is because scon
build system hasn't compiled the CommMonitor code. You should see this as a
WARNING during scon build process that protobuf iss missing. SCON checks for
google protocol buffer on your system and if scon doesn't find it then
'have_protobuf' is set to '0' and CommMonitor is not included in the build
repo. You have to install google protobuf then set PROTOC environment
variable to the installed dir. 
Post by Ahmad Hassan
scons -j6  build/X86/gem5.opt
This time scon will build all the CommMonitor classes and you won't see
any errors like '"NameError: global name 'CommMonitor' is not defined"'
Post by Ahmad Hassan
Caution: I set the PROTOC environ variable in the shell but still scon
doesn't pick it up. One way of getting around this is to change SConstruct
and provide the protoc path as '/usr/bin/protoc' instead of reading from
Post by Ahmad Hassan
('PROTOC', 'protoc tool', "/usr/bin/protoc"),   
Hope this helps.
Best Regards, Ahmad
On 11 February 2014 00:20, Aditya Deshpande <adityamdeshpande <at>
Ahmad,Thanks for the info. I had tried adding in similar way. After adding
these lines, I need to recompile the code. During recompilation, it gives me
an error
Post by Ahmad Hassan
"NameError: global name 'CommMonitor' is not defined"
Any pointers on how you got over this error. Did you add any header files
in src/cpu/BaseCPU.py
Post by Ahmad Hassan
Regards,Aditya
On Mon, Feb 10, 2014 at 9:21 AM, Ahmad Hassan <ahmad.hassan <at>
Hi Aditya,
Thank for the email. i added commmonitor between cpu and L1
in src/cpu/BaseCPU.py as follows
Post by Ahmad Hassan
        #self.dcache_port = dc.cpu_side
        self.L1MONITOR = CommMonitor(trace_file="L1");
        self.dcache_port = self.L1MONITOR.slave
        self.L1MONITOR.master = dc.cpu_side
Good luck.
Best Regards, Ahmad
On 10 February 2014 17:03, Aditya Deshpande <adityamdeshpande <at>
Ahmed,
If you want to add CommMonitor between l1 and L2 cache
In CacheConfig.py
Comment following linessystem.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
Add following linessystem.monitor2 =
CommMonitor(trace_file="CT_mon2.txt")system.monitor2.slave =
system.tol2bus.mastersystem.l2.cpu_side = system.monitor2.master
Post by Ahmad Hassan
system.l2.mem_side = system.membus.slave
The following lines basically changes the hierarchy from (l1-cache ->
tol2bus -> L2 Cache ->membus) to (l1cache -> tol2bus -> commMonitor monitor2
-> l2cache -> membus)
Post by Ahmad Hassan
I ran into same problem of CommMonitor being not found when i try to add
commMonitor between CPU and L1D-cache.
Post by Ahmad Hassan
Did you try to add any CommMonitor there? Any ideas on how to do that.
Regards,Aditya
On Sun, Feb 9, 2014 at 1:38 AM, Ahmad Hassan <ahmad.hassan <at> gmail.com>
HI Aditya,
How did you attach commonitor to L2 in 
config/common/CacheConfig.py. I get import errors if I try to import 'from
CommMonitor import *" in CacheConfig.py
Post by Ahmad Hassan
Please can you share the syntax of attaching L2 and L1 to commmonitor. 
Thanks.
On 31 January 2014 21:33, Aditya Deshpande <adityamdeshpande <at>
Andreas,
I understand how to add CommMonitor.  I was able to trace L2 cache
accesses using CommMonitor. In that case, I was adding commMonitor in
config/common/CacheConfig.py
Post by Ahmad Hassan
I was able to run the simulation and get the trace. The commMonitor
connections also showed in config.ini file
Post by Ahmad Hassan
Now given that interface between CPU and L1 cache is set in
/src/cpu/BaseCPU.py In that file when I add commMonitor between cpu
dcache_port and L1dcache cpu_side nothing happens. The simulation completes
but I don't see a trace file for this commMonitor, nor do I see any info
regarding this commMonitor in config.ini file.
Post by Ahmad Hassan
when adding commMonitor in /src/cpu/BaseCPU.py do I need to rebuilt the
system by running scons command before execution?
Post by Ahmad Hassan
Regards,Aditya
_______________________________________________
gem5-users mailing listgem5-users <at>
gem5.orghttp://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Post by Ahmad Hassan
_______________________________________________
gem5-users mailing list
gem5-users <at> gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Hi, I followed this thread and add the CommMonitor between the CPU and the
L1D cache and get result is -se as following:
r,401136,4,57000
w,401136,4,115000
w,401132,4,118000
r,2220,4,121000
w,401128,4,136000
......

I tried to follow the source code but get a little confused. Can any one
tell me what does each column stand for?

To my understanding, the first column is R/W operation. The second stands
for the address, the third is how many bytes the operation is and the last
is the cpu ticks of the packet. Is that right?
Andreas Hansson
2014-02-15 15:19:58 UTC
Permalink
Hi Pei,

The easiest is to have a look at the util/decode_packet_trace.py script.
The script merely prints a few of the fields. I¹d suggest you have a look
at src/proto/packet.proto for an extensive list if what fields are encoded
in the trace. The intention is not to use the python script for anything
besides quick checks.

If you want to analyze or in any way play back the trace, then use the
parsers generated by protoc (as done by util/decode_packet_trace.py for
Python or src/proto/protoio.cc for C++). That way you get the entire data
structure exposed through proper structs.

Andreas
Post by Ahmad Hassan
Post by Ahmad Hassan
Hi Andreas,
Yes you are right, If 'protoc' is in the path then SCONS picks it up
automatically.
Post by Ahmad Hassan
You need to add 'from CommMonitor import *' in src/cpu/BaseCPU.py to get
CommMonitor module there. If that doesn't fix your problem then please can
you verify if 'build/X86/config/have_protobuf.hh' shows '#define
HAVE_PROTOBUF 1'
Post by Ahmad Hassan
Best Regards, Ahmad
On 11 February 2014 16:50, Aditya Deshpande <adityamdeshpande <at>
Ahmad / Andreas,
I had installed protobuf before. Still get the error when I add
CommMonitor in /src/cpu/BaseCPU.py file. Enclosed is the log for
compilation and execution dump.
Post by Ahmad Hassan
oneloa 785% scons -j 8 build/X86_MESI_Two_Level/gem5.optscons: Reading
SConscript files ...Checking for leading underscore in global
variables...(cached) noChecking for C header file Python.h... (cached) yes
Post by Ahmad Hassan
Checking for C library pthread... (cached) yesChecking for C library dl...
(cached) yesChecking for C library util... (cached) yesChecking for C
library m... (cached) yesChecking for C library python2.6... (cached) yes
Post by Ahmad Hassan
Checking for accept(0,0,0) in C++ library None... (cached) yesChecking for
zlibVersion() in C++ library z... (cached) yesChecking for
GOOGLE_PROTOBUF_VERIFY_VERSION in C++ library protobuf... (cached)
yesChecking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached) no
Post by Ahmad Hassan
Checking for clock_nanosleep(0,0,NULL,NULL) in C library rt... (cached)
yesChecking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library
None... (cached) yesChecking for C library tcmalloc... (cached) yes
Post by Ahmad Hassan
Checking for C header file fenv.h... (cached) yesChecking for C header
file linux/kvm.h... (cached) yesChecking size of struct kvm_xsave ...
(cached) yesChecking for member exclude_host in struct
perf_event_attr...(cached) yes
Post by Ahmad Hassan
Reading SConsoptsBuilding in
/nfs/div1/adeshpan/arch/gem5/build/X86_MESI_Two_LevelUsing saved variables
done reading SConscript files.scons: warning: Support for pre-2.7.0 Python
version (2.6.6) is deprecated. If this will cause hardship, contact dev
<at> scons.tigris.org.File "/usr/ucb/scons", line 192, in <module>
Post by Ahmad Hassan
scons: Building targets ... [SO PARAM] BaseCPU ->
X86_MESI_Two_Level/params/BaseCPU.hh [ SO SWIG] BaseCPU ->
X86_MESI_Two_Level/python/m5/internal/param_BaseCPU.i [EMBED PY]
X86_MESI_Two_Level/cpu/BaseCPU.py -> .cc
Post by Ahmad Hassan
[ CXX]
X86_MESI_Two_Level/python/m5/internal/param_BaseSimpleCPU_wrap.cc ->
.o [ CXX]
X86_MESI_Two_Level/python/m5/internal/param_TimingSimpleCPU_wrap.cc ->
.o [ CXX]
X86_MESI_Two_Level/python/m5/internal/param_DummyChecker_wrap.cc -> .o
Post by Ahmad Hassan
[ CXX]
X86_MESI_Two_Level/python/m5/internal/param_CheckerCPU_wrap.cc
-> .o [ CXX]
X86_MESI_Two_Level/python/m5/internal/param_O3Checker_wrap.cc -> .o [
CXX] X86_MESI_Two_Level/python/m5/internal/param_AtomicSimpleCPU_wrap.cc -> .o
Post by Ahmad Hassan
[ CXX] X86_MESI_Two_Level/python/m5/internal/param_BaseCPU_wrap.cc ->
.o [ CXX]
X86_MESI_Two_Level/python/m5/internal/param_BaseKvmCPU_wrap.cc
-> .o [ CXX]
X86_MESI_Two_Level/python/m5/internal/param_DerivO3CPU_wrap.cc -> .o
Post by Ahmad Hassan
[ CXX]
X86_MESI_Two_Level/python/m5/internal/param_X86KvmCPU_wrap.cc
-> .oscons: `build/X86_MESI_Two_Level/gem5.opt' is up to date.scons: done
building targets.oneloa 786% ./build/X86_MESI_Two_Level/gem5.opt -v -d
/nfs/data-nas1/adeshpan/gem5 --debug-start=0 --debug-file=comm1.txt.gz
--debug-flags=Cache,CommMonitor,CachePort,Flag1AD
--stats-file=comm1stats.txt configs/example/se.py --caches
--cpu-type=TimingSimpleCPU --num-cpus=1 --l2cache --cpu-clock=1GHz -c
tests/test-progs/hello/bin/x86/linux/hello
Post by Ahmad Hassan
gem5 Simulator System. http://gem5.orggem5 is copyrighted software; use
the --copyright option for details.gem5 compiled Feb 11 2014 08:19:42gem5
started Feb 11 2014 08:45:13
./build/X86_MESI_Two_Level/gem5.opt -v -d /nfs/data-nas1/adeshpan/gem5
--debug-start=0 --debug-file=comm1.txt.gz
--debug-flags=Cache,CommMonitor,CachePort,Flag1AD
--stats-file=comm1stats.txt configs/example/se.py --caches
--cpu-type=TimingSimpleCPU --num-cpus=1 --l2cache --cpu-clock=1GHz -c
tests/test-progs/hello/bin/x86/linux/hello
Post by Ahmad Hassan
Traceback (most recent call last): File "<string>", line 1, in
<module>
File "/nfs/div1/adeshpan/arch/gem5/src/python/m5/main.py", line 388, in
main exec filecode in scope
Post by Ahmad Hassan
File "configs/example/se.py", line 254, in <module>
CacheConfig.config_cache(options, system) File
"/nfs/div1/adeshpan/arch/gem5/configs/common/CacheConfig.py", line 93, in
config_cache
Post by Ahmad Hassan
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(), PageTableWalkerCache()) File
"/nfs/div1/adeshpan/arch/gem5/src/cpu/BaseCPU.py", line 274, in
addPrivateSplitL1Caches self.monitor3 = CommMonitor(trace_file
="CT_mon3.ptrc")
Post by Ahmad Hassan
NameError: global name 'CommMonitor' is not defined
Anything else I can try? I tried adding the CommMonitor files in the
src/cpu folder, that also doesn't seem to work.
Post by Ahmad Hassan
Regards,Aditya
On Tue, Feb 11, 2014 at 3:36 AM, Ahmad Hassan <ahmad.hassan <at>
Hi Aditiya,
[Putting on the list so other people can benefit too]
It is not required to add any 'include' header in
src/cpu/BaseCPU.py. The reason you are getting this error is because scon
build system hasn't compiled the CommMonitor code. You should see this as a
WARNING during scon build process that protobuf iss missing. SCON checks for
google protocol buffer on your system and if scon doesn't find it then
'have_protobuf' is set to '0' and CommMonitor is not included in the build
repo. You have to install google protobuf then set PROTOC environment
variable to the installed dir.
Post by Ahmad Hassan
scons -j6 build/X86/gem5.opt
This time scon will build all the CommMonitor classes and you won't see
any errors like '"NameError: global name 'CommMonitor' is not defined"'
Post by Ahmad Hassan
Caution: I set the PROTOC environ variable in the shell but still scon
doesn't pick it up. One way of getting around this is to change SConstruct
and provide the protoc path as '/usr/bin/protoc' instead of reading from
Post by Ahmad Hassan
('PROTOC', 'protoc tool', "/usr/bin/protoc"),
Hope this helps.
Best Regards, Ahmad
On 11 February 2014 00:20, Aditya Deshpande <adityamdeshpande <at>
Ahmad,Thanks for the info. I had tried adding in similar way. After adding
these lines, I need to recompile the code. During recompilation, it gives me
an error
Post by Ahmad Hassan
"NameError: global name 'CommMonitor' is not defined"
Any pointers on how you got over this error. Did you add any header files
in src/cpu/BaseCPU.py
Post by Ahmad Hassan
Regards,Aditya
On Mon, Feb 10, 2014 at 9:21 AM, Ahmad Hassan <ahmad.hassan <at>
Hi Aditya,
Thank for the email. i added commmonitor between cpu and L1
in src/cpu/BaseCPU.py as follows
Post by Ahmad Hassan
#self.dcache_port = dc.cpu_side
self.L1MONITOR = CommMonitor(trace_file="L1");
self.dcache_port = self.L1MONITOR.slave
self.L1MONITOR.master = dc.cpu_side
Good luck.
Best Regards, Ahmad
On 10 February 2014 17:03, Aditya Deshpande <adityamdeshpande <at>
Ahmed,
If you want to add CommMonitor between l1 and L2 cache
In CacheConfig.py
Comment following linessystem.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
Add following linessystem.monitor2 =
CommMonitor(trace_file="CT_mon2.txt")system.monitor2.slave =
system.tol2bus.mastersystem.l2.cpu_side = system.monitor2.master
Post by Ahmad Hassan
system.l2.mem_side = system.membus.slave
The following lines basically changes the hierarchy from (l1-cache ->
tol2bus -> L2 Cache ->membus) to (l1cache -> tol2bus -> commMonitor monitor2
-> l2cache -> membus)
Post by Ahmad Hassan
I ran into same problem of CommMonitor being not found when i try to add
commMonitor between CPU and L1D-cache.
Post by Ahmad Hassan
Did you try to add any CommMonitor there? Any ideas on how to do that.
Regards,Aditya
On Sun, Feb 9, 2014 at 1:38 AM, Ahmad Hassan <ahmad.hassan <at> gmail.com>
HI Aditya,
How did you attach commonitor to L2 in
config/common/CacheConfig.py. I get import errors if I try to import 'from
CommMonitor import *" in CacheConfig.py
Post by Ahmad Hassan
Please can you share the syntax of attaching L2 and L1 to commmonitor.
Thanks.
On 31 January 2014 21:33, Aditya Deshpande <adityamdeshpande <at>
Andreas,
I understand how to add CommMonitor. I was able to trace L2 cache
accesses using CommMonitor. In that case, I was adding commMonitor in
config/common/CacheConfig.py
Post by Ahmad Hassan
I was able to run the simulation and get the trace. The commMonitor
connections also showed in config.ini file
Post by Ahmad Hassan
Now given that interface between CPU and L1 cache is set in
/src/cpu/BaseCPU.py In that file when I add commMonitor between cpu
dcache_port and L1dcache cpu_side nothing happens. The simulation completes
but I don't see a trace file for this commMonitor, nor do I see any info
regarding this commMonitor in config.ini file.
Post by Ahmad Hassan
when adding commMonitor in /src/cpu/BaseCPU.py do I need to rebuilt the
system by running scons command before execution?
Post by Ahmad Hassan
Regards,Aditya
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Post by Ahmad Hassan
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Hi, I followed this thread and add the CommMonitor between the CPU and the
r,401136,4,57000
w,401136,4,115000
w,401132,4,118000
r,2220,4,121000
w,401128,4,136000
......
I tried to follow the source code but get a little confused. Can any one
tell me what does each column stand for?
To my understanding, the first column is R/W operation. The second stands
for the address, the third is how many bytes the operation is and the last
is the cpu ticks of the packet. Is that right?
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Aditya Deshpande
2014-02-10 17:13:26 UTC
Permalink
If you generate the debug trace or log file for the transaction, you would
observe all the ReadReq, ReadResp, WriteReq, WriteResp packets. You can do
that by adding following flags to your execution commands

--debug-start=<start_time> --debug-file=<filename.txt.gz>
--debug-flags=Cache

Use the .gz option as the file size gets very large. Or you can define your
custom flags and reduce the filesize.

Regards,
Aditya
Aditya Deshpande
2014-02-11 20:39:23 UTC
Permalink
Ahmad,

Adding

'from CommMonitor import *' in src/cpu/BaseCPU.py

worked.

Thanks.

Regards,
Aditya
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