Discussion:
fatal error cpu does not have any master port
(too old to reply)
ignacio charalabidis
2013-04-18 09:25:59 UTC
Permalink
I am getting this error:

fatal: system.secondmainCpu does not have any master port named second_dcache_port
@ cycle 0
[getMasterPort:build/ARM/mem/mem_object.cc, line 54]

However, in my config file I do see the port:

[system.secondmainCpu]
children=dcache dtb fuPool icache interrupts isa itb second_dcache second_icache tracer
...
dcache_port=system.secondmainCpu.dcache.cpu_side
icache_port=system.secondmainCpu.icache.cpu_side
second_dcache_port=system.secondmainCpu.second_dcache.second_cpu_side
second_icache_port=system.secondmainCpu.second_icache.second_cpu_side

and the way I declare it in my code is this:

in my BaseCache.py

cpu_side = SlavePort("Port on side closer to CPU")
mem_side = MasterPort("Port on side closer to MEM")
second_mem_side = MasterPort("Second Port on side closer to MEM")
second_cpu_side = SlavePort("Port on side closer to second CPU")

and in my BaseCpu.py

def addPrivateSplitL1Caches(self, ic, dc, second_ic, second_dc,iwc = None, dwc = None):
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self.second_icache = second_ic
self.second_dcache = second_dc
self.second_icache_port = second_ic.second_cpu_side
self.second_dcache_port = second_dc.second_cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side','second_icache.second_mem_side','second_dcache.second_mem_side']


Why that happens? I just copied the code for the first port in order to create a new one.

Thanks,
Ignatios
Andreas Hansson
2013-04-18 10:19:26 UTC
Permalink
You need to also get the C++ code to recognise it and return the right port ref.

You have updated the Python code, but there is still no port to match it in the C++ object.

Andreas

From: ignacio charalabidis <***@hotmail.com<mailto:***@hotmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Thursday, 18 April 2013 04:25
To: "gem5-***@gem5.org<mailto:gem5-***@gem5.org>" <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: [gem5-users] fatal error cpu does not have any master port

I am getting this error:

fatal: system.secondmainCpu does not have any master port named second_dcache_port
@ cycle 0
[getMasterPort:build/ARM/mem/mem_object.cc, line 54]

However, in my config file I do see the port:

[system.secondmainCpu]
children=dcache dtb fuPool icache interrupts isa itb second_dcache second_icache tracer
...
dcache_port=system.secondmainCpu.dcache.cpu_side
icache_port=system.secondmainCpu.icache.cpu_side
second_dcache_port=system.secondmainCpu.second_dcache.second_cpu_side
second_icache_port=system.secondmainCpu.second_icache.second_cpu_side

and the way I declare it in my code is this:

in my BaseCache.py

cpu_side = SlavePort("Port on side closer to CPU")
mem_side = MasterPort("Port on side closer to MEM")
second_mem_side = MasterPort("Second Port on side closer to MEM")
second_cpu_side = SlavePort("Port on side closer to second CPU")

and in my BaseCpu.py

def addPrivateSplitL1Caches(self, ic, dc, second_ic, second_dc,iwc = None, dwc = None):
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self.second_icache = second_ic
self.second_dcache = second_dc
self.second_icache_port = second_ic.second_cpu_side
self.second_dcache_port = second_dc.second_cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side','second_icache.second_mem_side','second_dcache.second_mem_side']


Why that happens? I just copied the code for the first port in order to create a new one.

Thanks,
Ignatios





-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
ignacio charalabidis
2013-04-18 13:44:41 UTC
Permalink
Thank Andrea,

So I changed in the base.cc into this:

if ((if_name == "dcache_port") || (if_name == "second_dcache_port"))
return getDataPort();
else if ((if_name == "icache_port") || (if_name == "dcache_port"))
return getInstrPort();


and also added the same for the cache.

Is that all?

And one more question? Should I change my getDataPort to return masterPort or can I leave it to return cpuPort? Will it make any difference?

Because now my program gets aborted at cycle0 so I have missed something.

Thanks,
Ignatios

From: ***@arm.com
To: gem5-***@gem5.org
Date: Thu, 18 Apr 2013 11:19:26 +0100
Subject: Re: [gem5-users] fatal error cpu does not have any master port






You need to also get the C++ code to recognise it and return the right port ref.



You have updated the Python code, but there is still no port to match it in the C++ object.



Andreas





From: ignacio charalabidis <***@hotmail.com>

Reply-To: gem5 users mailing list <gem5-***@gem5.org>

Date: Thursday, 18 April 2013 04:25

To: "gem5-***@gem5.org" <gem5-***@gem5.org>

Subject: [gem5-users] fatal error cpu does not have any master port







I am getting this error:



fatal: system.secondmainCpu does not have any master port named second_dcache_port

@ cycle 0

[getMasterPort:build/ARM/mem/mem_object.cc, line 54]



However, in my config file I do see the port:



[system.secondmainCpu]

children=dcache dtb fuPool icache interrupts isa itb second_dcache second_icache tracer

...

dcache_port=system.secondmainCpu.dcache.cpu_side

icache_port=system.secondmainCpu.icache.cpu_side

second_dcache_port=system.secondmainCpu.second_dcache.second_cpu_side

second_icache_port=system.secondmainCpu.second_icache.second_cpu_side



and the way I declare it in my code is this:



in my BaseCache.py



cpu_side = SlavePort("Port on side closer to CPU")

mem_side = MasterPort("Port on side closer to MEM")

second_mem_side = MasterPort("Second Port on side closer to MEM")

second_cpu_side = SlavePort("Port on side closer to second CPU")



and in my BaseCpu.py



def addPrivateSplitL1Caches(self, ic, dc, second_ic, second_dc,iwc = None, dwc = None):

self.icache = ic

self.dcache = dc

self.icache_port = ic.cpu_side

self.dcache_port = dc.cpu_side

self.second_icache = second_ic

self.second_dcache = second_dc

self.second_icache_port = second_ic.second_cpu_side

self.second_dcache_port = second_dc.second_cpu_side

self._cached_ports = ['icache.mem_side', 'dcache.mem_side','second_icache.second_mem_side','second_dcache.second_mem_side']





Why that happens? I just copied the code for the first port in order to create a new one.



Thanks,

Ignatios














-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents
to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Andreas Hansson
2013-04-18 13:48:38 UTC
Permalink
You have to create a new port, not just hand over the same one. This change is rather complex in fact. Once the extra port is there you also have to make use of the two ports and somehow distribute the outgoing requests and keep the view between the two coherent.

Andreas

From: ignacio charalabidis <***@hotmail.com<mailto:***@hotmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Thursday, 18 April 2013 14:44
To: "gem5-***@gem5.org<mailto:gem5-***@gem5.org>" <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] fatal error cpu does not have any master port

Thank Andrea,

So I changed in the base.cc into this:


if ((if_name == "dcache_port") || (if_name == "second_dcache_port")) return getDataPort();
else if ((if_name == "icache_port") || (if_name == "dcache_port"))
return getInstrPort();


and also added the same for the cache.


Is that all?

And one more question? Should I change my getDataPort to return masterPort or can I leave it to return cpuPort? Will it make any difference?

Because now my program gets aborted at cycle0 so I have missed something.

Thanks,
Ignatios

________________________________
From: ***@arm.com<mailto:***@arm.com>
To: gem5-***@gem5.org<mailto:gem5-***@gem5.org>
Date: Thu, 18 Apr 2013 11:19:26 +0100
Subject: Re: [gem5-users] fatal error cpu does not have any master port

You need to also get the C++ code to recognise it and return the right port ref.

You have updated the Python code, but there is still no port to match it in the C++ object.

Andreas

From: ignacio charalabidis <***@hotmail.com<mailto:***@hotmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Thursday, 18 April 2013 04:25
To: "gem5-***@gem5.org<mailto:gem5-***@gem5.org>" <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: [gem5-users] fatal error cpu does not have any master port

I am getting this error:

fatal: system.secondmainCpu does not have any master port named second_dcache_port
@ cycle 0
[getMasterPort:build/ARM/mem/mem_object.cc, line 54]

However, in my config file I do see the port:

[system.secondmainCpu]
children=dcache dtb fuPool icache interrupts isa itb second_dcache second_icache tracer
...
dcache_port=system.secondmainCpu.dcache.cpu_side
icache_port=system.secondmainCpu.icache.cpu_side
second_dcache_port=system.secondmainCpu.second_dcache.second_cpu_side
second_icache_port=system.secondmainCpu.second_icache.second_cpu_side

and the way I declare it in my code is this:

in my BaseCache.py

cpu_side = SlavePort("Port on side closer to CPU")
mem_side = MasterPort("Port on side closer to MEM")
second_mem_side = MasterPort("Second Port on side closer to MEM")
second_cpu_side = SlavePort("Port on side closer to second CPU")

and in my BaseCpu.py

def addPrivateSplitL1Caches(self, ic, dc, second_ic, second_dc,iwc = None, dwc = None):
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self.second_icache = second_ic
self.second_dcache = second_dc
self.second_icache_port = second_ic.second_cpu_side
self.second_dcache_port = second_dc.second_cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side','second_icache.second_mem_side','second_dcache.second_mem_side']


Why that happens? I just copied the code for the first port in order to create a new one.

Thanks,
Ignatios





-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

_______________________________________________ gem5-users mailing list gem5-***@gem5.org<mailto:gem5-***@gem5.org> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
ignacio charalabidis
2013-04-19 09:36:39 UTC
Permalink
Thanks again Andrea for your reply. Can you give me some guidance on that? I do not find any material that I should look into :/
Besides the implementation,I have a more important question at the end of the mail.

For example, to begin with the creation of the new port:

in cpu.hh file I see this definition:

virtual CpuPort &getDataPort() { return dcachePort; }

So the way I have it right now, will always return dcachePort and I have to change it in something like this:

virtual CpuPort &getSecondDataPort() { return second_dcachePort; } ?

and add in the cpu.hh this:

DcachePort second_dcacheport;

and in the cpu.cc

dcachePort(&iew.ldstQueue, this),

inside the FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)

Is it more what I need to do for creation of the port ?

And more important, if you can answer on that, because if the answer is negative then the above do not have a special meaning. I want to have 2 caches for the following reason. I want to keep both of the caches attached to a core, in order to keep them both of them warm all the time. Actually, imagine like a 2x2 grid where I am having 2 cpus with its own private cache. But I want when cpuA is running, and cpuB is switched_out, to keep the cache of cpuB warm. So I thought that I could send the request also in that cpu, and in order to do so I need to define another one port in my cpu and in my cache. Does it make sense? Is the approach correct?

Hope you can answer on that,
Regards,
Ignatios

From: ***@arm.com
To: gem5-***@gem5.org
Date: Thu, 18 Apr 2013 14:48:38 +0100
Subject: Re: [gem5-users] fatal error cpu does not have any master port






You have to create a new port, not just hand over the same one. This change is rather complex in fact. Once the extra port is there you also have to make use of the two ports and somehow distribute the outgoing requests and keep the view between the two
coherent.



Andreas





From: ignacio charalabidis <***@hotmail.com>

Reply-To: gem5 users mailing list <gem5-***@gem5.org>

Date: Thursday, 18 April 2013 14:44

To: "gem5-***@gem5.org" <gem5-***@gem5.org>

Subject: Re: [gem5-users] fatal error cpu does not have any master port







Thank Andrea,



So I changed in the base.cc into this:



if ((if_name == "dcache_port") || (if_name == "second_dcache_port")) return getDataPort();
else if ((if_name == "icache_port") || (if_name == "dcache_port"))
return getInstrPort();


and also added the same for the cache.


Is that all?



And one more question? Should I change my getDataPort to return masterPort or can I leave it to return cpuPort? Will it make any difference?




Because now my program gets aborted at cycle0 so I have missed something.



Thanks,

Ignatios






From: ***@arm.com

To: gem5-***@gem5.org

Date: Thu, 18 Apr 2013 11:19:26 +0100

Subject: Re: [gem5-users] fatal error cpu does not have any master port



You need to also get the C++ code to recognise it and return the right port ref.



You have updated the Python code, but there is still no port to match it in the C++ object.



Andreas





From: ignacio charalabidis <***@hotmail.com>

Reply-To: gem5 users mailing list <gem5-***@gem5.org>

Date: Thursday, 18 April 2013 04:25

To: "gem5-***@gem5.org" <gem5-***@gem5.org>

Subject: [gem5-users] fatal error cpu does not have any master port







I am getting this error:



fatal: system.secondmainCpu does not have any master port named second_dcache_port

@ cycle 0

[getMasterPort:build/ARM/mem/mem_object.cc, line 54]



However, in my config file I do see the port:



[system.secondmainCpu]

children=dcache dtb fuPool icache interrupts isa itb second_dcache second_icache tracer

...

dcache_port=system.secondmainCpu.dcache.cpu_side

icache_port=system.secondmainCpu.icache.cpu_side

second_dcache_port=system.secondmainCpu.second_dcache.second_cpu_side

second_icache_port=system.secondmainCpu.second_icache.second_cpu_side



and the way I declare it in my code is this:



in my BaseCache.py



cpu_side = SlavePort("Port on side closer to CPU")

mem_side = MasterPort("Port on side closer to MEM")

second_mem_side = MasterPort("Second Port on side closer to MEM")

second_cpu_side = SlavePort("Port on side closer to second CPU")



and in my BaseCpu.py



def addPrivateSplitL1Caches(self, ic, dc, second_ic, second_dc,iwc = None, dwc = None):

self.icache = ic

self.dcache = dc

self.icache_port = ic.cpu_side

self.dcache_port = dc.cpu_side

self.second_icache = second_ic

self.second_dcache = second_dc

self.second_icache_port = second_ic.second_cpu_side

self.second_dcache_port = second_dc.second_cpu_side

self._cached_ports = ['icache.mem_side', 'dcache.mem_side','second_icache.second_mem_side','second_dcache.second_mem_side']





Why that happens? I just copied the code for the first port in order to create a new one.



Thanks,

Ignatios














-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents
to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.



_______________________________________________ gem5-users mailing list
gem5-***@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users





-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents
to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
ignacio charalabidis
2013-04-21 13:41:59 UTC
Permalink
Thanks Andrea,

> You have to create a new port, not just hand over the same one

Ok I created a new port also in the .cc file that I needed. Now the system is set up correctly as i can see in the config file.

Now for my second_icache_port for example I am receiving some panic messages during warm-up like this one:
panic: system.cpu.second_icache_port was not expecting a timing snoop request
@ cycle 159000

while using the --debug-flag=Cache,CachePort,CacheRepl I get these:

151000: system.cpu.icache: set 5b: moving blk 496c0 to MRU
151000: system.cpu.icache: ReadReq (ifetch) 496d4 hit
151000: system.cpu.icache: set 5b: moving blk 496c0 to MRU
151000: system.cpu.icache: ReadReq (ifetch) 496c0 hit
158000: system.cpu.icache: ReadReq (ifetch) 49700 miss
158000: system.cpu.icache.mem_side: Asserting bus request for cause 0

>you also have to make use of the two ports and somehow distribute the outgoing requests

Can you give me a hint on where to look at because I am lost. For example,
-where are these requests for example. I am not sure why for example it is the second_icache_port that was not expecting the timing snoop request and not the icache_port (because it works if I do not add the second_icache_port) since they are of the same type (ICachePort).

Thanks,
Ignatios


From: ***@arm.com
To: gem5-***@gem5.org
Date: Thu, 18 Apr 2013 14:48:38 +0100
Subject: Re: [gem5-users] fatal error cpu does not have any master port






You have to create a new port, not just hand over the same one. This change is rather complex in fact. Once the extra port is there you also have to make use of the two ports and somehow distribute the outgoing requests and keep the view between the two
coherent.



Andreas
Andreas Hansson
2013-04-21 15:42:42 UTC
Permalink
Hi Ignatios,

I think this topic is far beyond the "user" list and even quite a deep dive for the "dev" list.

The short answer is: You cannot simply use another instance of the same subclass of the port as it is tied to the LSQ and fetch unit and the port calls them, and they call the port. Thus, when you add a new port it is just dangling on the side in the C++ world.

The longer answer: Figure out what it is you really want to do, e.g. spread the load between two cache ports? Is this really the easiest way of doing it. If the purpose is to have multiple ports, why not make it a vector port to start with? In any of these cases, you will need to do a significant amount of changes to the O3 CPU, the LSQ, the fetch unit, the caches etc. I'm happy to look at a patch, but ultimately you'll have to familiarise yourself with all the aforementioned bits and pieces.

Andreas

From: ignacio charalabidis <***@hotmail.com<mailto:***@hotmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Sunday, 21 April 2013 14:41
To: "gem5-***@gem5.org<mailto:gem5-***@gem5.org>" <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] fatal error cpu does not have any master port

Thanks Andrea,

> You have to create a new port, not just hand over the same one

Ok I created a new port also in the .cc file that I needed. Now the system is set up correctly as i can see in the config file.

Now for my second_icache_port for example I am receiving some panic messages during warm-up like this one:
panic: system.cpu.second_icache_port was not expecting a timing snoop request
@ cycle 159000

while using the --debug-flag=Cache,CachePort,CacheRepl I get these:

151000: system.cpu.icache: set 5b: moving blk 496c0 to MRU
151000: system.cpu.icache: ReadReq (ifetch) 496d4 hit
151000: system.cpu.icache: set 5b: moving blk 496c0 to MRU
151000: system.cpu.icache: ReadReq (ifetch) 496c0 hit
158000: system.cpu.icache: ReadReq (ifetch) 49700 miss
158000: system.cpu.icache.mem_side: Asserting bus request for cause 0

>you also have to make use of the two ports and somehow distribute the outgoing requests

Can you give me a hint on where to look at because I am lost. For example,
-where are these requests for example. I am not sure why for example it is the second_icache_port that was not expecting the timing snoop request and not the icache_port (because it works if I do not add the second_icache_port) since they are of the same type (ICachePort).

Thanks,
Ignatios


________________________________
From: ***@arm.com<mailto:***@arm.com>
To: gem5-***@gem5.org<mailto:gem5-***@gem5.org>
Date: Thu, 18 Apr 2013 14:48:38 +0100
Subject: Re: [gem5-users] fatal error cpu does not have any master port

You have to create a new port, not just hand over the same one. This change is rather complex in fact. Once the extra port is there you also have to make use of the two ports and somehow distribute the outgoing requests and keep the view between the two coherent.

Andreas


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
ignacio charalabidis
2013-04-21 15:54:47 UTC
Permalink
Thanks Andrea for your reply. Ok I will try to figure it out or think a different way and not spam the list again for that topic.

Basically I would be happy if you can advice me on that:

I am having 2 cpus with private L1 caches. What I am doing so far in my simulation is changing the workload from one cpu to another, without unbinding/binding the caches that was happening earlier in the switchCpus function. So every interval, my workload run in a a different cpu. The way I understand it so far, is that when the cpu is switched_out then the caches are kept coherent, but not warm.

Now, I want to extend that and to be able to keep my cache warm. And I thought one way of doing so was to have two ports, instead of one (so each cpu is connected with the two caches) and duplicate every request to the "cache of the idle cpu".

So let me give you an example:
Lets assume I am having 32kb caches. My workload is working on an array of 32kB, so it fits in the cache. Then I switch from core B to core A.
Now cache A also gets filled up with the data. However, say the workload moves on to a second array of 32kB. Slowly cache A fills up with the second
array, but cache B still holds the first array and nothing from the second. I think this is what happening now and this is what I mean "kept cold". What I want
is to keep cacheB warm --with the data of the second array in my example, even if its cpu was idle.

Regards,
Ignatios


From: ***@arm.com
To: gem5-***@gem5.org
Date: Sun, 21 Apr 2013 16:42:42 +0100
Subject: Re: [gem5-users] fatal error cpu does not have any master port






Hi Ignatios,



I think this topic is far beyond the "user" list and even quite a deep dive for the "dev" list.



The short answer is: You cannot simply use another instance of the same subclass of the port as it is tied to the LSQ and fetch unit and the port calls them, and they call the port. Thus, when you add a new port it is just dangling on the side in the C++
world.



The longer answer: Figure out what it is you really want to do, e.g. spread the load between two cache ports? Is this really the easiest way of doing it. If the purpose is to have multiple ports, why not make it a vector port to start with? In any of these
cases, you will need to do a significant amount of changes to the O3 CPU, the LSQ, the fetch unit, the caches etc. I'm happy to look at a patch, but ultimately you'll have to familiarise yourself with all the aforementioned bits and pieces.



Andreas





From: ignacio charalabidis <***@hotmail.com>

Reply-To: gem5 users mailing list <gem5-***@gem5.org>

Date: Sunday, 21 April 2013 14:41

To: "gem5-***@gem5.org" <gem5-***@gem5.org>

Subject: Re: [gem5-users] fatal error cpu does not have any master port








Thanks Andrea,



> You have to create a new port, not just hand over the same one



Ok I created a new port also in the .cc file that I needed. Now the system is set up correctly as i can see in the config file.



Now for my second_icache_port for example I am receiving some panic messages during warm-up like this one:

panic: system.cpu.second_icache_port was not expecting a timing snoop request

@ cycle 159000



while using the --debug-flag=Cache,CachePort,CacheRepl I get these:



151000: system.cpu.icache: set 5b: moving blk 496c0 to MRU

151000: system.cpu.icache: ReadReq (ifetch) 496d4 hit

151000: system.cpu.icache: set 5b: moving blk 496c0 to MRU

151000: system.cpu.icache: ReadReq (ifetch) 496c0 hit

158000: system.cpu.icache: ReadReq (ifetch) 49700 miss

158000: system.cpu.icache.mem_side: Asserting bus request for cause 0



>you also have to make use of the two ports and somehow distribute the outgoing requests



Can you give me a hint on where to look at because I am lost. For example,

-where are these requests for example. I am not sure why for example it is the second_icache_port that was not expecting the timing snoop request and not the icache_port (because it works if I do not add the second_icache_port) since they are of the same type
(ICachePort).



Thanks,

Ignatios







From: ***@arm.com

To: gem5-***@gem5.org

Date: Thu, 18 Apr 2013 14:48:38 +0100

Subject: Re: [gem5-users] fatal error cpu does not have any master port



You have to create a new port, not just hand over the same one. This change is rather complex in fact. Once the extra port is there you also have to make use of the two ports and somehow distribute the outgoing requests and keep the view between the two
coherent.



Andreas









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