Discussion:
question on test code compilation
(too old to reply)
Jiayuan Meng
2007-05-15 18:18:58 UTC
Permalink
Hi all,

I am a starter on M5, and I'm interested in simulating a multithreaded program on a CMP architecture. My question is, can M5 run programs written with pthreads? what crosscompiler do you recommend to compile C or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?

I tried to compile helloworld code on UltraSparc IIIi/SunOS using gcc version 3.3.6. However, the sparc binary generates faults when the code is run on M5. Would you please give me some hints?

Thanks!

Jiayuan
Steve Reinhardt
2007-05-15 18:38:46 UTC
Permalink
M5 can run pthreads binaries in full-system mode, which means you're
restricted to Alpha for now.

There are directions on building a gcc-based cross compiler here:

http://www.m5sim.org/wiki/index.php/Using_linux-dist_to_Create_Disk_Images_and_Kernels_for_M5

Note that you just need to follow the first section (on building the
cross compiler); the other parts on building a new kernel are
unnecessary if you're just compiling new applications.

Steve
Post by Jiayuan Meng
Hi all,
I am a starter on M5, and I'm interested in simulating a multithreaded
program on a CMP architecture. My question is, can M5 run programs
written with pthreads? what crosscompiler do you recommend to compile C
or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?
I tried to compile helloworld code on UltraSparc IIIi/SunOS using gcc
version 3.3.6. However, the sparc binary generates faults when the code
is run on M5. Would you please give me some hints?
Thanks!
Jiayuan
------------------------------------------------------------------------
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Jiayuan
2007-05-15 21:05:43 UTC
Permalink
Thanks a lot Steve!

I am trying to model a CMP architecture. I think at this stage, I will not
model OS. I would prefer to run with syscall emulation mode. So I have two
following questions:

1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/example,
se.py has only one SimpleCPU configured)

2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
simulator. There might be other primitives as well. This may involve: adding
more ops to the ISA, adding a load balancer unit to the simulator that
creates threads (allocate stack size, set per-thread stack pointers, passing
thread contexts). Would you please give some hints on how to implement these
in M5?

Thanks!

Jiayuan

-----Original Message-----
From: m5-users-***@m5sim.org [mailto:m5-users-***@m5sim.org] On
Behalf Of Steve Reinhardt
Sent: Tuesday, May 15, 2007 2:39 PM
To: M5 users mailing list
Subject: Re: [m5-users] question on test code compilation

M5 can run pthreads binaries in full-system mode, which means you're
restricted to Alpha for now.

There are directions on building a gcc-based cross compiler here:

http://www.m5sim.org/wiki/index.php/Using_linux-dist_to_Create_Disk_Images_a
nd_Kernels_for_M5

Note that you just need to follow the first section (on building the
cross compiler); the other parts on building a new kernel are
unnecessary if you're just compiling new applications.

Steve
Post by Jiayuan Meng
Hi all,
I am a starter on M5, and I'm interested in simulating a multithreaded
program on a CMP architecture. My question is, can M5 run programs
written with pthreads? what crosscompiler do you recommend to compile C
or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?
I tried to compile helloworld code on UltraSparc IIIi/SunOS using gcc
version 3.3.6. However, the sparc binary generates faults when the code
is run on M5. Would you please give me some hints?
Thanks!
Jiayuan
------------------------------------------------------------------------
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
g***@eecs.umich.edu
2007-05-16 03:36:30 UTC
Permalink
One thing I noticed is that you said you compiled your binaries on a SunOS
machine. SPARC SE only supports Linux binaries at the moment, so you'll need to
recompile. Also, SPARC support is not totally production ready right now, so you
could quite possibly run into problems which are not your fault. If you need
something that's very likely to work, I would recommend using Alpha. If you
decide to use SPARC, please let us know of any bugs you might find and/or fix.

Gabe
Post by Jiayuan
Thanks a lot Steve!
I am trying to model a CMP architecture. I think at this stage, I will not
model OS. I would prefer to run with syscall emulation mode. So I have two
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/example,
se.py has only one SimpleCPU configured)
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
simulator. There might be other primitives as well. This may involve: adding
more ops to the ISA, adding a load balancer unit to the simulator that
creates threads (allocate stack size, set per-thread stack pointers, passing
thread contexts). Would you please give some hints on how to implement these
in M5?
Thanks!
Jiayuan
-----Original Message-----
Behalf Of Steve Reinhardt
Sent: Tuesday, May 15, 2007 2:39 PM
To: M5 users mailing list
Subject: Re: [m5-users] question on test code compilation
M5 can run pthreads binaries in full-system mode, which means you're
restricted to Alpha for now.
http://www.m5sim.org/wiki/index.php/Using_linux-dist_to_Create_Disk_Images_a
nd_Kernels_for_M5
Note that you just need to follow the first section (on building the
cross compiler); the other parts on building a new kernel are
unnecessary if you're just compiling new applications.
Steve
Post by Jiayuan Meng
Hi all,
I am a starter on M5, and I'm interested in simulating a multithreaded
program on a CMP architecture. My question is, can M5 run programs
written with pthreads? what crosscompiler do you recommend to compile C
or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?
I tried to compile helloworld code on UltraSparc IIIi/SunOS using gcc
version 3.3.6. However, the sparc binary generates faults when the code
is run on M5. Would you please give me some hints?
Thanks!
Jiayuan
------------------------------------------------------------------------
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Jiayuan
2007-05-17 03:19:58 UTC
Permalink
Thanks Gabe! So Alpha is the choice at this time.

But I'm still fuzzy on the CMP simulation with M5.

1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/example,
se.py has only one SimpleCPU configured)

2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
simulator. There might be other primitives as well. This may involve:
adding more ops to the ISA, adding a load balancer unit to the simulator
that creates threads (allocate stack size, set per-thread stack pointers,
passing thread contexts). Would you please give some hints on how to
implement these in M5?

3. How Flexible is the memory system? In se.py, private L1 caches are
specified, and I saw in BaseCPU.py that a private L2 cache can also be
added, but what if I want to have private L1 caches for each core and a
shared L2 cache?

4. How fast is M5? How many instructions can M5 run in one second on
average?

5. Why the test case radix doesn't work under ALPHA_SE, and instead it
prints out:
warn: loadGlobalSymbols: bad symbol header magic on
tests/test-progs/radix/bin/radix
warn: Entering event queue @ 0. Starting simulation...
warn: ignoring syscall sigprocmask(3, 18446744073709551615, ...)
warn: ignoring syscall sigprocmask(3, 0, ...)
warn: ignoring syscall sigaction(8, 4831387552, ...)
warn: ignoring syscall sigaction(11, 4831387552, ...)
warn: ignoring syscall sigaction(10, 4831387552, ...)
warn: ignoring syscall sigaction(4, 4831387552, ...)
warn: ignoring syscall sigaction(7, 4831387552, ...)
warn: ignoring syscall sigaction(6, 4831387552, ...)
warn: ignoring syscall sigaction(12, 4831387552, ...)
warn: ignoring syscall sigaction(5, 4831387552, ...)
warn: ignoring syscall sigaction(13, 4831387552, ...)

Thanks!

Jiayuan



-----Original Message-----
From: ***@eecs.umich.edu [mailto:***@eecs.umich.edu]
Sent: Tuesday, May 15, 2007 11:37 PM
To: M5 users mailing list; Jiayuan
Subject: Re: CMP simulation in SE mode + RE: [m5-users] question on test
code compilation

One thing I noticed is that you said you compiled your binaries on a
SunOS
machine. SPARC SE only supports Linux binaries at the moment, so you'll need
to
recompile. Also, SPARC support is not totally production ready right now, so
you
could quite possibly run into problems which are not your fault. If you need
something that's very likely to work, I would recommend using Alpha. If you
decide to use SPARC, please let us know of any bugs you might find and/or
fix.

Gabe
Post by Jiayuan
Thanks a lot Steve!
I am trying to model a CMP architecture. I think at this stage, I will not
model OS. I would prefer to run with syscall emulation mode. So I have two
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/example,
se.py has only one SimpleCPU configured)
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
simulator. There might be other primitives as well. This may involve: adding
more ops to the ISA, adding a load balancer unit to the simulator that
creates threads (allocate stack size, set per-thread stack pointers, passing
thread contexts). Would you please give some hints on how to implement these
in M5?
Thanks!
Jiayuan
-----Original Message-----
Behalf Of Steve Reinhardt
Sent: Tuesday, May 15, 2007 2:39 PM
To: M5 users mailing list
Subject: Re: [m5-users] question on test code compilation
M5 can run pthreads binaries in full-system mode, which means you're
restricted to Alpha for now.
http://www.m5sim.org/wiki/index.php/Using_linux-dist_to_Create_Disk_Images_a
Post by Jiayuan
nd_Kernels_for_M5
Note that you just need to follow the first section (on building the
cross compiler); the other parts on building a new kernel are
unnecessary if you're just compiling new applications.
Steve
Post by Jiayuan Meng
Hi all,
I am a starter on M5, and I'm interested in simulating a multithreaded
program on a CMP architecture. My question is, can M5 run programs
written with pthreads? what crosscompiler do you recommend to compile C
or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?
I tried to compile helloworld code on UltraSparc IIIi/SunOS using gcc
version 3.3.6. However, the sparc binary generates faults when the code
is run on M5. Would you please give me some hints?
Thanks!
Jiayuan
------------------------------------------------------------------------
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Ronald George Dreslinski Jr
2007-05-17 03:36:58 UTC
Permalink
Post by Jiayuan
Thanks Gabe! So Alpha is the choice at this time.
But I'm still fuzzy on the CMP simulation with M5.
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/example,
se.py has only one SimpleCPU configured)
Yes it is possible to simulate a CMP in SE mode. It is easy to simulate a
multiprogrammed workload where each core is running it's own process. If
you want a configuration that supports a multi-threaded program you will
need to modify things to handle it. If you are looking to use pthreads I
would suggest moving to FS mode. As for an example config there isn't one
in the release tree. You could look at the configs in the configs/splash2
directory and modify it to assign each CPU it's own workload.
Post by Jiayuan
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
adding more ops to the ISA, adding a load balancer unit to the simulator
that creates threads (allocate stack size, set per-thread stack pointers,
passing thread contexts). Would you please give some hints on how to
implement these in M5?
You could look at the way we implemented the Splash2 benchmarks in SE mode
for an example, but again it might be easier to move to FS mode for
multi-threaded workloads. Please see the email discussion with Edith Hand
about the Splash2 benchmarks for patches that make the Splash2 benchmarks
work and a config file that is up to date.
Post by Jiayuan
3. How Flexible is the memory system? In se.py, private L1 caches are
specified, and I saw in BaseCPU.py that a private L2 cache can also be
added, but what if I want to have private L1 caches for each core and a
shared L2 cache?
It is flexible enough to instantiate a private L1 and a shared L2 cache.
See the configs/splash2/run.py file for how that is set up properly.
Post by Jiayuan
4. How fast is M5? How many instructions can M5 run in one second on
average?
This depends greatly on the configuration. It runs faster if you use
atomic mode and ignore the timing. If you are using the simpleCPU it will
simulate faster than the O3 CPU. I don;t have numbers around regarding
how common configs will run or how the number of Cores changes those
values. Perhaps someone else in the group has some recent data on the
simulation rates of common configs.
Post by Jiayuan
Post by Jiayuan
5. Why the test case radix doesn't work under ALPHA_SE, and instead it
warn: loadGlobalSymbols: bad symbol header magic on
tests/test-progs/radix/bin/radix
warn: ignoring syscall sigprocmask(3, 18446744073709551615, ...)
warn: ignoring syscall sigprocmask(3, 0, ...)
warn: ignoring syscall sigaction(8, 4831387552, ...)
warn: ignoring syscall sigaction(11, 4831387552, ...)
warn: ignoring syscall sigaction(10, 4831387552, ...)
warn: ignoring syscall sigaction(4, 4831387552, ...)
warn: ignoring syscall sigaction(7, 4831387552, ...)
warn: ignoring syscall sigaction(6, 4831387552, ...)
warn: ignoring syscall sigaction(12, 4831387552, ...)
warn: ignoring syscall sigaction(5, 4831387552, ...)
warn: ignoring syscall sigaction(13, 4831387552, ...)
This isn't broken. It is just a warning that gets printed out, but
doesn't cause incorrect behavior of the code. Does anything print out
after this that indacates a failure? Perhaps a abort, segfault, panic,
...
Post by Jiayuan
Thanks!
Jiayuan
Hope that helps clarify things a little further,
-Ron
Post by Jiayuan
-----Original Message-----
Sent: Tuesday, May 15, 2007 11:37 PM
To: M5 users mailing list; Jiayuan
Subject: Re: CMP simulation in SE mode + RE: [m5-users] question on test
code compilation
One thing I noticed is that you said you compiled your binaries on a
SunOS
machine. SPARC SE only supports Linux binaries at the moment, so you'll need
to
recompile. Also, SPARC support is not totally production ready right now, so
you
could quite possibly run into problems which are not your fault. If you need
something that's very likely to work, I would recommend using Alpha. If you
decide to use SPARC, please let us know of any bugs you might find and/or
fix.
Gabe
Post by Jiayuan
Thanks a lot Steve!
I am trying to model a CMP architecture. I think at this stage, I will not
model OS. I would prefer to run with syscall emulation mode. So I have two
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/example,
se.py has only one SimpleCPU configured)
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
adding
Post by Jiayuan
more ops to the ISA, adding a load balancer unit to the simulator that
creates threads (allocate stack size, set per-thread stack pointers,
passing
Post by Jiayuan
thread contexts). Would you please give some hints on how to implement
these
Post by Jiayuan
in M5?
Thanks!
Jiayuan
-----Original Message-----
Behalf Of Steve Reinhardt
Sent: Tuesday, May 15, 2007 2:39 PM
To: M5 users mailing list
Subject: Re: [m5-users] question on test code compilation
M5 can run pthreads binaries in full-system mode, which means you're
restricted to Alpha for now.
http://www.m5sim.org/wiki/index.php/Using_linux-dist_to_Create_Disk_Images_a
Post by Jiayuan
nd_Kernels_for_M5
Note that you just need to follow the first section (on building the
cross compiler); the other parts on building a new kernel are
unnecessary if you're just compiling new applications.
Steve
Post by Jiayuan Meng
Hi all,
I am a starter on M5, and I'm interested in simulating a multithreaded
program on a CMP architecture. My question is, can M5 run programs
written with pthreads? what crosscompiler do you recommend to compile C
or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?
I tried to compile helloworld code on UltraSparc IIIi/SunOS using gcc
version 3.3.6. However, the sparc binary generates faults when the code
is run on M5. Would you please give me some hints?
Thanks!
Jiayuan
------------------------------------------------------------------------
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Jiayuan
2007-05-17 04:26:00 UTC
Permalink
Hey Ron,

Thank you so much! This helps me a lot and establishes further my confidence
in M5 :) COOL!

Radix did finish executing, despite the warnings, I just want to make sure
that the system call is handled (maybe a bit confused by the printing that
says "ignoring system call ..."). I'm curious about what kind of system
calls is ignored.

I'm excited about configs/splash2, but I cannot find it in m5-2.0b3
directory after I unpack the tar ball... Is it in this released version?
Post by Ronald George Dreslinski Jr
Please see the email discussion with Edith Hand
about the Splash2 benchmarks for patches that make the Splash2 benchmarks
work and a config file that is up to date
Sorry about another dummy's question: where can I find this discussion? (I
just subscribed to the m5 user mailing list...)

Thank you so much!

Jiayuan

-----Original Message-----
From: m5-users-***@m5sim.org [mailto:m5-users-***@m5sim.org] On
Behalf Of Ronald George Dreslinski Jr
Sent: Wednesday, May 16, 2007 11:37 PM
To: M5 users mailing list
Subject: Re: [m5-users] CMP simulation in SE mode
Post by Ronald George Dreslinski Jr
Thanks Gabe! So Alpha is the choice at this time.
But I'm still fuzzy on the CMP simulation with M5.
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/example,
se.py has only one SimpleCPU configured)
Yes it is possible to simulate a CMP in SE mode. It is easy to simulate a
multiprogrammed workload where each core is running it's own process. If
you want a configuration that supports a multi-threaded program you will
need to modify things to handle it. If you are looking to use pthreads I
would suggest moving to FS mode. As for an example config there isn't one
in the release tree. You could look at the configs in the configs/splash2
directory and modify it to assign each CPU it's own workload.
Post by Ronald George Dreslinski Jr
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
adding more ops to the ISA, adding a load balancer unit to the simulator
that creates threads (allocate stack size, set per-thread stack pointers,
passing thread contexts). Would you please give some hints on how to
implement these in M5?
You could look at the way we implemented the Splash2 benchmarks in SE mode
for an example, but again it might be easier to move to FS mode for
multi-threaded workloads. Please see the email discussion with Edith Hand
about the Splash2 benchmarks for patches that make the Splash2 benchmarks
work and a config file that is up to date.
Post by Ronald George Dreslinski Jr
3. How Flexible is the memory system? In se.py, private L1 caches are
specified, and I saw in BaseCPU.py that a private L2 cache can also be
added, but what if I want to have private L1 caches for each core and a
shared L2 cache?
It is flexible enough to instantiate a private L1 and a shared L2 cache.
See the configs/splash2/run.py file for how that is set up properly.
Post by Ronald George Dreslinski Jr
4. How fast is M5? How many instructions can M5 run in one second on
average?
This depends greatly on the configuration. It runs faster if you use
atomic mode and ignore the timing. If you are using the simpleCPU it will
simulate faster than the O3 CPU. I don;t have numbers around regarding
how common configs will run or how the number of Cores changes those
values. Perhaps someone else in the group has some recent data on the
simulation rates of common configs.
Post by Ronald George Dreslinski Jr
Post by Jiayuan
5. Why the test case radix doesn't work under ALPHA_SE, and instead it
warn: loadGlobalSymbols: bad symbol header magic on
tests/test-progs/radix/bin/radix
warn: ignoring syscall sigprocmask(3, 18446744073709551615, ...)
warn: ignoring syscall sigprocmask(3, 0, ...)
warn: ignoring syscall sigaction(8, 4831387552, ...)
warn: ignoring syscall sigaction(11, 4831387552, ...)
warn: ignoring syscall sigaction(10, 4831387552, ...)
warn: ignoring syscall sigaction(4, 4831387552, ...)
warn: ignoring syscall sigaction(7, 4831387552, ...)
warn: ignoring syscall sigaction(6, 4831387552, ...)
warn: ignoring syscall sigaction(12, 4831387552, ...)
warn: ignoring syscall sigaction(5, 4831387552, ...)
warn: ignoring syscall sigaction(13, 4831387552, ...)
This isn't broken. It is just a warning that gets printed out, but
doesn't cause incorrect behavior of the code. Does anything print out
after this that indacates a failure? Perhaps a abort, segfault, panic,
...
Post by Ronald George Dreslinski Jr
Thanks!
Jiayuan
Hope that helps clarify things a little further,
-Ron
Post by Ronald George Dreslinski Jr
-----Original Message-----
Sent: Tuesday, May 15, 2007 11:37 PM
To: M5 users mailing list; Jiayuan
Subject: Re: CMP simulation in SE mode + RE: [m5-users] question on test
code compilation
One thing I noticed is that you said you compiled your binaries on a
SunOS
machine. SPARC SE only supports Linux binaries at the moment, so you'll need
to
recompile. Also, SPARC support is not totally production ready right now, so
you
could quite possibly run into problems which are not your fault. If you need
something that's very likely to work, I would recommend using Alpha. If you
decide to use SPARC, please let us know of any bugs you might find and/or
fix.
Gabe
Post by Jiayuan
Thanks a lot Steve!
I am trying to model a CMP architecture. I think at this stage, I will not
model OS. I would prefer to run with syscall emulation mode. So I have two
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/example,
se.py has only one SimpleCPU configured)
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
adding
Post by Jiayuan
more ops to the ISA, adding a load balancer unit to the simulator that
creates threads (allocate stack size, set per-thread stack pointers,
passing
Post by Jiayuan
thread contexts). Would you please give some hints on how to implement
these
Post by Jiayuan
in M5?
Thanks!
Jiayuan
-----Original Message-----
Behalf Of Steve Reinhardt
Sent: Tuesday, May 15, 2007 2:39 PM
To: M5 users mailing list
Subject: Re: [m5-users] question on test code compilation
M5 can run pthreads binaries in full-system mode, which means you're
restricted to Alpha for now.
http://www.m5sim.org/wiki/index.php/Using_linux-dist_to_Create_Disk_Images_a
Post by Ronald George Dreslinski Jr
Post by Jiayuan
nd_Kernels_for_M5
Note that you just need to follow the first section (on building the
cross compiler); the other parts on building a new kernel are
unnecessary if you're just compiling new applications.
Steve
Post by Jiayuan Meng
Hi all,
I am a starter on M5, and I'm interested in simulating a multithreaded
program on a CMP architecture. My question is, can M5 run programs
written with pthreads? what crosscompiler do you recommend to compile C
or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?
I tried to compile helloworld code on UltraSparc IIIi/SunOS using gcc
version 3.3.6. However, the sparc binary generates faults when the code
is run on M5. Would you please give me some hints?
Thanks!
Jiayuan
------------------------------------------------------------------------
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Ali Saidi
2007-05-17 13:19:06 UTC
Permalink
Post by Jiayuan
Hey Ron,
Thank you so much! This helps me a lot and establishes further my confidence
in M5 :) COOL!
Radix did finish executing, despite the warnings, I just want to make sure
that the system call is handled (maybe a bit confused by the
printing that
says "ignoring system call ..."). I'm curious about what kind of system
calls is ignored.
I'm excited about configs/splash2, but I cannot find it in m5-2.0b3
directory after I unpack the tar ball... Is it in this released version?
Post by Ronald George Dreslinski Jr
Please see the email discussion with Edith Hand
about the Splash2 benchmarks for patches that make the Splash2 benchmarks
work and a config file that is up to date
Sorry about another dummy's question: where can I find this
discussion? (I
just subscribed to the m5 user mailing list...)
There on the M5 website to two services which archive all the mails
on this mailing list.

Ali
Post by Jiayuan
Thank you so much!
Jiayuan
-----Original Message-----
Behalf Of Ronald George Dreslinski Jr
Sent: Wednesday, May 16, 2007 11:37 PM
To: M5 users mailing list
Subject: Re: [m5-users] CMP simulation in SE mode
Post by Ronald George Dreslinski Jr
Thanks Gabe! So Alpha is the choice at this time.
But I'm still fuzzy on the CMP simulation with M5.
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
Yes it is possible to simulate a CMP in SE mode. It is easy to simulate a
multiprogrammed workload where each core is running it's own
process. If
you want a configuration that supports a multi-threaded program you will
need to modify things to handle it. If you are looking to use
pthreads I
would suggest moving to FS mode. As for an example config there isn't one
in the release tree. You could look at the configs in the configs/
splash2
directory and modify it to assign each CPU it's own workload.
Post by Ronald George Dreslinski Jr
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
adding more ops to the ISA, adding a load balancer unit to the simulator
that creates threads (allocate stack size, set per-thread stack pointers,
passing thread contexts). Would you please give some hints on how to
implement these in M5?
You could look at the way we implemented the Splash2 benchmarks in SE mode
for an example, but again it might be easier to move to FS mode for
multi-threaded workloads. Please see the email discussion with
Edith Hand
about the Splash2 benchmarks for patches that make the Splash2
benchmarks
work and a config file that is up to date.
Post by Ronald George Dreslinski Jr
3. How Flexible is the memory system? In se.py, private L1 caches are
specified, and I saw in BaseCPU.py that a private L2 cache can also be
added, but what if I want to have private L1 caches for each core and a
shared L2 cache?
It is flexible enough to instantiate a private L1 and a shared L2 cache.
See the configs/splash2/run.py file for how that is set up properly.
Post by Ronald George Dreslinski Jr
4. How fast is M5? How many instructions can M5 run in one second on
average?
This depends greatly on the configuration. It runs faster if you use
atomic mode and ignore the timing. If you are using the simpleCPU it will
simulate faster than the O3 CPU. I don;t have numbers around
regarding
how common configs will run or how the number of Cores changes those
values. Perhaps someone else in the group has some recent data on the
simulation rates of common configs.
Post by Ronald George Dreslinski Jr
Post by Jiayuan
5. Why the test case radix doesn't work under ALPHA_SE, and
instead it
warn: loadGlobalSymbols: bad symbol header magic on
tests/test-progs/radix/bin/radix
warn: ignoring syscall sigprocmask(3, 18446744073709551615, ...)
warn: ignoring syscall sigprocmask(3, 0, ...)
warn: ignoring syscall sigaction(8, 4831387552, ...)
warn: ignoring syscall sigaction(11, 4831387552, ...)
warn: ignoring syscall sigaction(10, 4831387552, ...)
warn: ignoring syscall sigaction(4, 4831387552, ...)
warn: ignoring syscall sigaction(7, 4831387552, ...)
warn: ignoring syscall sigaction(6, 4831387552, ...)
warn: ignoring syscall sigaction(12, 4831387552, ...)
warn: ignoring syscall sigaction(5, 4831387552, ...)
warn: ignoring syscall sigaction(13, 4831387552, ...)
This isn't broken. It is just a warning that gets printed out, but
doesn't cause incorrect behavior of the code. Does anything print out
after this that indacates a failure? Perhaps a abort, segfault, panic,
...
Post by Ronald George Dreslinski Jr
Thanks!
Jiayuan
Hope that helps clarify things a little further,
-Ron
Post by Ronald George Dreslinski Jr
-----Original Message-----
Sent: Tuesday, May 15, 2007 11:37 PM
To: M5 users mailing list; Jiayuan
Subject: Re: CMP simulation in SE mode + RE: [m5-users] question on test
code compilation
One thing I noticed is that you said you compiled your binaries on a
SunOS
machine. SPARC SE only supports Linux binaries at the moment, so
you'll
need
Post by Ronald George Dreslinski Jr
to
recompile. Also, SPARC support is not totally production ready
right now,
so
Post by Ronald George Dreslinski Jr
you
could quite possibly run into problems which are not your fault.
If you
need
Post by Ronald George Dreslinski Jr
something that's very likely to work, I would recommend using
Alpha. If
you
Post by Ronald George Dreslinski Jr
decide to use SPARC, please let us know of any bugs you might find and/or
fix.
Gabe
Post by Jiayuan
Thanks a lot Steve!
I am trying to model a CMP architecture. I think at this stage, I
will
not
Post by Ronald George Dreslinski Jr
Post by Jiayuan
model OS. I would prefer to run with syscall emulation mode. So I
have
two
Post by Ronald George Dreslinski Jr
Post by Jiayuan
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
2. Since I have to run threads on this configuration with SE
mode, I will
need to implement some thread creation/termination primitives in the
simulator. There might be other primitives as well. This may
adding
Post by Jiayuan
more ops to the ISA, adding a load balancer unit to the simulator that
creates threads (allocate stack size, set per-thread stack pointers,
passing
Post by Jiayuan
thread contexts). Would you please give some hints on how to
implement
these
Post by Jiayuan
in M5?
Thanks!
Jiayuan
-----Original Message-----
Behalf Of Steve Reinhardt
Sent: Tuesday, May 15, 2007 2:39 PM
To: M5 users mailing list
Subject: Re: [m5-users] question on test code compilation
M5 can run pthreads binaries in full-system mode, which means you're
restricted to Alpha for now.
http://www.m5sim.org/wiki/index.php/Using_linux-
dist_to_Create_Disk_Images_a
Post by Ronald George Dreslinski Jr
Post by Jiayuan
nd_Kernels_for_M5
Note that you just need to follow the first section (on building the
cross compiler); the other parts on building a new kernel are
unnecessary if you're just compiling new applications.
Steve
Post by Jiayuan Meng
Hi all,
I am a starter on M5, and I'm interested in simulating a
multithreaded
program on a CMP architecture. My question is, can M5 run programs
written with pthreads? what crosscompiler do you recommend to compile C
or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?
I tried to compile helloworld code on UltraSparc IIIi/SunOS
using gcc
version 3.3.6. However, the sparc binary generates faults when the code
is run on M5. Would you please give me some hints?
Thanks!
Jiayuan
-------------------------------------------------------------------
-----
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Jiayuan
2007-05-17 17:31:30 UTC
Permalink
Thanks a lot Ali :)

Jiayuan

-----Original Message-----
From: m5-users-***@m5sim.org [mailto:m5-users-***@m5sim.org] On
Behalf Of Ali Saidi
Sent: Thursday, May 17, 2007 9:19 AM
To: M5 users mailing list
Subject: Re: [m5-users] CMP simulation in SE mode
Post by Jiayuan
Hey Ron,
Thank you so much! This helps me a lot and establishes further my confidence
in M5 :) COOL!
Radix did finish executing, despite the warnings, I just want to make sure
that the system call is handled (maybe a bit confused by the
printing that
says "ignoring system call ..."). I'm curious about what kind of system
calls is ignored.
I'm excited about configs/splash2, but I cannot find it in m5-2.0b3
directory after I unpack the tar ball... Is it in this released version?
Post by Ronald George Dreslinski Jr
Please see the email discussion with Edith Hand
about the Splash2 benchmarks for patches that make the Splash2 benchmarks
work and a config file that is up to date
Sorry about another dummy's question: where can I find this
discussion? (I
just subscribed to the m5 user mailing list...)
There on the M5 website to two services which archive all the mails
on this mailing list.

Ali
Post by Jiayuan
Thank you so much!
Jiayuan
-----Original Message-----
Behalf Of Ronald George Dreslinski Jr
Sent: Wednesday, May 16, 2007 11:37 PM
To: M5 users mailing list
Subject: Re: [m5-users] CMP simulation in SE mode
Post by Ronald George Dreslinski Jr
Thanks Gabe! So Alpha is the choice at this time.
But I'm still fuzzy on the CMP simulation with M5.
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
Yes it is possible to simulate a CMP in SE mode. It is easy to simulate a
multiprogrammed workload where each core is running it's own
process. If
you want a configuration that supports a multi-threaded program you will
need to modify things to handle it. If you are looking to use
pthreads I
would suggest moving to FS mode. As for an example config there isn't one
in the release tree. You could look at the configs in the configs/
splash2
directory and modify it to assign each CPU it's own workload.
Post by Ronald George Dreslinski Jr
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
adding more ops to the ISA, adding a load balancer unit to the simulator
that creates threads (allocate stack size, set per-thread stack pointers,
passing thread contexts). Would you please give some hints on how to
implement these in M5?
You could look at the way we implemented the Splash2 benchmarks in SE mode
for an example, but again it might be easier to move to FS mode for
multi-threaded workloads. Please see the email discussion with
Edith Hand
about the Splash2 benchmarks for patches that make the Splash2
benchmarks
work and a config file that is up to date.
Post by Ronald George Dreslinski Jr
3. How Flexible is the memory system? In se.py, private L1 caches are
specified, and I saw in BaseCPU.py that a private L2 cache can also be
added, but what if I want to have private L1 caches for each core and a
shared L2 cache?
It is flexible enough to instantiate a private L1 and a shared L2 cache.
See the configs/splash2/run.py file for how that is set up properly.
Post by Ronald George Dreslinski Jr
4. How fast is M5? How many instructions can M5 run in one second on
average?
This depends greatly on the configuration. It runs faster if you use
atomic mode and ignore the timing. If you are using the simpleCPU it will
simulate faster than the O3 CPU. I don;t have numbers around
regarding
how common configs will run or how the number of Cores changes those
values. Perhaps someone else in the group has some recent data on the
simulation rates of common configs.
Post by Ronald George Dreslinski Jr
Post by Jiayuan
5. Why the test case radix doesn't work under ALPHA_SE, and
instead it
warn: loadGlobalSymbols: bad symbol header magic on
tests/test-progs/radix/bin/radix
warn: ignoring syscall sigprocmask(3, 18446744073709551615, ...)
warn: ignoring syscall sigprocmask(3, 0, ...)
warn: ignoring syscall sigaction(8, 4831387552, ...)
warn: ignoring syscall sigaction(11, 4831387552, ...)
warn: ignoring syscall sigaction(10, 4831387552, ...)
warn: ignoring syscall sigaction(4, 4831387552, ...)
warn: ignoring syscall sigaction(7, 4831387552, ...)
warn: ignoring syscall sigaction(6, 4831387552, ...)
warn: ignoring syscall sigaction(12, 4831387552, ...)
warn: ignoring syscall sigaction(5, 4831387552, ...)
warn: ignoring syscall sigaction(13, 4831387552, ...)
This isn't broken. It is just a warning that gets printed out, but
doesn't cause incorrect behavior of the code. Does anything print out
after this that indacates a failure? Perhaps a abort, segfault, panic,
...
Post by Ronald George Dreslinski Jr
Thanks!
Jiayuan
Hope that helps clarify things a little further,
-Ron
Post by Ronald George Dreslinski Jr
-----Original Message-----
Sent: Tuesday, May 15, 2007 11:37 PM
To: M5 users mailing list; Jiayuan
Subject: Re: CMP simulation in SE mode + RE: [m5-users] question on test
code compilation
One thing I noticed is that you said you compiled your binaries on a
SunOS
machine. SPARC SE only supports Linux binaries at the moment, so
you'll
need
Post by Ronald George Dreslinski Jr
to
recompile. Also, SPARC support is not totally production ready
right now,
so
Post by Ronald George Dreslinski Jr
you
could quite possibly run into problems which are not your fault.
If you
need
Post by Ronald George Dreslinski Jr
something that's very likely to work, I would recommend using
Alpha. If
you
Post by Ronald George Dreslinski Jr
decide to use SPARC, please let us know of any bugs you might find and/or
fix.
Gabe
Post by Jiayuan
Thanks a lot Steve!
I am trying to model a CMP architecture. I think at this stage, I
will
not
Post by Ronald George Dreslinski Jr
Post by Jiayuan
model OS. I would prefer to run with syscall emulation mode. So I
have
two
Post by Ronald George Dreslinski Jr
Post by Jiayuan
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
2. Since I have to run threads on this configuration with SE
mode, I will
need to implement some thread creation/termination primitives in the
simulator. There might be other primitives as well. This may
adding
Post by Jiayuan
more ops to the ISA, adding a load balancer unit to the simulator that
creates threads (allocate stack size, set per-thread stack pointers,
passing
Post by Jiayuan
thread contexts). Would you please give some hints on how to
implement
these
Post by Jiayuan
in M5?
Thanks!
Jiayuan
-----Original Message-----
Behalf Of Steve Reinhardt
Sent: Tuesday, May 15, 2007 2:39 PM
To: M5 users mailing list
Subject: Re: [m5-users] question on test code compilation
M5 can run pthreads binaries in full-system mode, which means you're
restricted to Alpha for now.
http://www.m5sim.org/wiki/index.php/Using_linux-
dist_to_Create_Disk_Images_a
Post by Ronald George Dreslinski Jr
Post by Jiayuan
nd_Kernels_for_M5
Note that you just need to follow the first section (on building the
cross compiler); the other parts on building a new kernel are
unnecessary if you're just compiling new applications.
Steve
Post by Jiayuan Meng
Hi all,
I am a starter on M5, and I'm interested in simulating a
multithreaded
program on a CMP architecture. My question is, can M5 run programs
written with pthreads? what crosscompiler do you recommend to compile C
or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?
I tried to compile helloworld code on UltraSparc IIIi/SunOS
using gcc
version 3.3.6. However, the sparc binary generates faults when the code
is run on M5. Would you please give me some hints?
Thanks!
Jiayuan
-------------------------------------------------------------------
-----
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Sujay Phadke
2007-05-17 18:53:34 UTC
Permalink
Hello,
I just started using M5. I am trying to compile the beta3. It gives the
following output:

scons: Reading SConscript files ...
Checking for C header file Python.h... (cached) yes
Checking for main() in C library python2.5... (cached) yes
Checking for accept(0,0,0) in C++ library None... (cached) yes
Checking for zlibVersion() in C++ library z... (cached) yes
Checking for C header file fenv.h... (cached) yes
Building in /n/rtcl20/home/sphadke/research/m5/m5-2.0b3/build/ALPHA_SE
Options file
/n/rtcl20/home/sphadke/research/m5/m5-2.0b3/build/options/ALPHA_SE not
found,
using defaults in build_opts/ALPHA_SE
scons: done reading SConscript files.
scons: Building targets ...

It does run thru and build finally, but hy does it not find the options
file? Is that required?

Also, I cannot build anything other than the debug. If I try opt on either
scons build/ALPHA_SE/m5.opt
scons: Reading SConscript files ...
Checking for C header file Python.h... (cached) yes
Checking for main() in C library python2.5... (cached) yes
Checking for accept(0,0,0) in C++ library None... (cached) yes
Checking for zlibVersion() in C++ library z... (cached) yes
Checking for C header file fenv.h... (cached) yes
Building in /n/rtcl20/home/sphadke/research/m5/m5-2.0b3/build/ALPHA_SE
Using saved options file
/n/rtcl20/home/sphadke/research/m5/m5-2.0b3/build/options/ALPHA_SE

scons: *** Error converting option: CPU_MODELS
Invalid value(s) for option: <built-in function all>
File "SConstruct", line 611, in <module>

- Sujay


----- Original Message -----
From: "Jiayuan" <***@hotmail.com>
To: "'M5 users mailing list'" <m5-***@m5sim.org>
Sent: Thursday, May 17, 2007 1:31 PM
Subject: RE: [m5-users] CMP simulation in SE mode
Thanks a lot Ali :)
Jiayuan
-----Original Message-----
Behalf Of Ali Saidi
Sent: Thursday, May 17, 2007 9:19 AM
To: M5 users mailing list
Subject: Re: [m5-users] CMP simulation in SE mode
Post by Jiayuan
Hey Ron,
Thank you so much! This helps me a lot and establishes further my confidence
in M5 :) COOL!
Radix did finish executing, despite the warnings, I just want to make sure
that the system call is handled (maybe a bit confused by the
printing that
says "ignoring system call ..."). I'm curious about what kind of system
calls is ignored.
I'm excited about configs/splash2, but I cannot find it in m5-2.0b3
directory after I unpack the tar ball... Is it in this released version?
Post by Ronald George Dreslinski Jr
Please see the email discussion with Edith Hand
about the Splash2 benchmarks for patches that make the Splash2 benchmarks
work and a config file that is up to date
Sorry about another dummy's question: where can I find this
discussion? (I
just subscribed to the m5 user mailing list...)
There on the M5 website to two services which archive all the mails
on this mailing list.
Ali
Post by Jiayuan
Thank you so much!
Jiayuan
-----Original Message-----
Behalf Of Ronald George Dreslinski Jr
Sent: Wednesday, May 16, 2007 11:37 PM
To: M5 users mailing list
Subject: Re: [m5-users] CMP simulation in SE mode
Post by Ronald George Dreslinski Jr
Thanks Gabe! So Alpha is the choice at this time.
But I'm still fuzzy on the CMP simulation with M5.
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
Yes it is possible to simulate a CMP in SE mode. It is easy to simulate a
multiprogrammed workload where each core is running it's own
process. If
you want a configuration that supports a multi-threaded program you will
need to modify things to handle it. If you are looking to use
pthreads I
would suggest moving to FS mode. As for an example config there isn't one
in the release tree. You could look at the configs in the configs/
splash2
directory and modify it to assign each CPU it's own workload.
Post by Ronald George Dreslinski Jr
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
adding more ops to the ISA, adding a load balancer unit to the simulator
that creates threads (allocate stack size, set per-thread stack pointers,
passing thread contexts). Would you please give some hints on how to
implement these in M5?
You could look at the way we implemented the Splash2 benchmarks in SE mode
for an example, but again it might be easier to move to FS mode for
multi-threaded workloads. Please see the email discussion with
Edith Hand
about the Splash2 benchmarks for patches that make the Splash2 benchmarks
work and a config file that is up to date.
Post by Ronald George Dreslinski Jr
3. How Flexible is the memory system? In se.py, private L1 caches are
specified, and I saw in BaseCPU.py that a private L2 cache can also be
added, but what if I want to have private L1 caches for each core and a
shared L2 cache?
It is flexible enough to instantiate a private L1 and a shared L2 cache.
See the configs/splash2/run.py file for how that is set up properly.
Post by Ronald George Dreslinski Jr
4. How fast is M5? How many instructions can M5 run in one second on
average?
This depends greatly on the configuration. It runs faster if you use
atomic mode and ignore the timing. If you are using the simpleCPU it will
simulate faster than the O3 CPU. I don;t have numbers around
regarding
how common configs will run or how the number of Cores changes those
values. Perhaps someone else in the group has some recent data on the
simulation rates of common configs.
Post by Ronald George Dreslinski Jr
Post by Jiayuan
5. Why the test case radix doesn't work under ALPHA_SE, and
instead it
warn: loadGlobalSymbols: bad symbol header magic on
tests/test-progs/radix/bin/radix
warn: ignoring syscall sigprocmask(3, 18446744073709551615, ...)
warn: ignoring syscall sigprocmask(3, 0, ...)
warn: ignoring syscall sigaction(8, 4831387552, ...)
warn: ignoring syscall sigaction(11, 4831387552, ...)
warn: ignoring syscall sigaction(10, 4831387552, ...)
warn: ignoring syscall sigaction(4, 4831387552, ...)
warn: ignoring syscall sigaction(7, 4831387552, ...)
warn: ignoring syscall sigaction(6, 4831387552, ...)
warn: ignoring syscall sigaction(12, 4831387552, ...)
warn: ignoring syscall sigaction(5, 4831387552, ...)
warn: ignoring syscall sigaction(13, 4831387552, ...)
This isn't broken. It is just a warning that gets printed out, but
doesn't cause incorrect behavior of the code. Does anything print out
after this that indacates a failure? Perhaps a abort, segfault, panic,
...
Post by Ronald George Dreslinski Jr
Thanks!
Jiayuan
Hope that helps clarify things a little further,
-Ron
Post by Ronald George Dreslinski Jr
-----Original Message-----
Sent: Tuesday, May 15, 2007 11:37 PM
To: M5 users mailing list; Jiayuan
Subject: Re: CMP simulation in SE mode + RE: [m5-users] question on test
code compilation
One thing I noticed is that you said you compiled your binaries on a
SunOS
machine. SPARC SE only supports Linux binaries at the moment, so
you'll
need
Post by Ronald George Dreslinski Jr
to
recompile. Also, SPARC support is not totally production ready
right now,
so
Post by Ronald George Dreslinski Jr
you
could quite possibly run into problems which are not your fault.
If you
need
Post by Ronald George Dreslinski Jr
something that's very likely to work, I would recommend using
Alpha. If
you
Post by Ronald George Dreslinski Jr
decide to use SPARC, please let us know of any bugs you might find and/or
fix.
Gabe
Post by Jiayuan
Thanks a lot Steve!
I am trying to model a CMP architecture. I think at this stage, I
will
not
Post by Ronald George Dreslinski Jr
Post by Jiayuan
model OS. I would prefer to run with syscall emulation mode. So I
have
two
Post by Ronald George Dreslinski Jr
Post by Jiayuan
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
adding
Post by Jiayuan
more ops to the ISA, adding a load balancer unit to the simulator that
creates threads (allocate stack size, set per-thread stack pointers,
passing
Post by Jiayuan
thread contexts). Would you please give some hints on how to
implement
these
Post by Jiayuan
in M5?
Thanks!
Jiayuan
-----Original Message-----
Behalf Of Steve Reinhardt
Sent: Tuesday, May 15, 2007 2:39 PM
To: M5 users mailing list
Subject: Re: [m5-users] question on test code compilation
M5 can run pthreads binaries in full-system mode, which means you're
restricted to Alpha for now.
http://www.m5sim.org/wiki/index.php/Using_linux-
dist_to_Create_Disk_Images_a
Post by Ronald George Dreslinski Jr
Post by Jiayuan
nd_Kernels_for_M5
Note that you just need to follow the first section (on building the
cross compiler); the other parts on building a new kernel are
unnecessary if you're just compiling new applications.
Steve
Post by Jiayuan Meng
Hi all,
I am a starter on M5, and I'm interested in simulating a
multithreaded
program on a CMP architecture. My question is, can M5 run programs
written with pthreads? what crosscompiler do you recommend to compile C
or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?
I tried to compile helloworld code on UltraSparc IIIi/SunOS
using gcc
version 3.3.6. However, the sparc binary generates faults when the code
is run on M5. Would you please give me some hints?
Thanks!
Jiayuan
-------------------------------------------------------------------
-----
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Steve Reinhardt
2007-05-17 19:09:47 UTC
Permalink
Post by Sujay Phadke
Hello,
I just started using M5. I am trying to compile the beta3. It gives
scons: Reading SConscript files ...
Checking for C header file Python.h... (cached) yes
Checking for main() in C library python2.5... (cached) yes
Checking for accept(0,0,0) in C++ library None... (cached) yes
Checking for zlibVersion() in C++ library z... (cached) yes
Checking for C header file fenv.h... (cached) yes
Building in /n/rtcl20/home/sphadke/research/m5/m5-2.0b3/build/ALPHA_SE
Options file
/n/rtcl20/home/sphadke/research/m5/m5-2.0b3/build/options/ALPHA_SE not
found,
using defaults in build_opts/ALPHA_SE
scons: done reading SConscript files.
scons: Building targets ...
It does run thru and build finally, but hy does it not find the options
file? Is that required?
It's just a standard notification the first time you build in a new
directory... it didn't find any saved build options from the last time
you built (since there was no last time), so it's initializing the saved
options with the default values. If this was actually an error it would
say "error" or something like that.

http://www.m5sim.org/wiki/index.php/Compiling_M5#Compiling
http://www.m5sim.org/wiki/index.php/SCons_build_system
Post by Sujay Phadke
Also, I cannot build anything other than the debug. If I try opt on
scons build/ALPHA_SE/m5.opt
scons: Reading SConscript files ...
Checking for C header file Python.h... (cached) yes
Checking for main() in C library python2.5... (cached) yes
Checking for accept(0,0,0) in C++ library None... (cached) yes
Checking for zlibVersion() in C++ library z... (cached) yes
Checking for C header file fenv.h... (cached) yes
Building in /n/rtcl20/home/sphadke/research/m5/m5-2.0b3/build/ALPHA_SE
Using saved options file
/n/rtcl20/home/sphadke/research/m5/m5-2.0b3/build/options/ALPHA_SE
scons: *** Error converting option: CPU_MODELS
Invalid value(s) for option: <built-in function all>
File "SConstruct", line 611, in <module>
It looks like it's having problems reloading the saved options... I'm
guessing this is just because it's the second time you've tried to build
something, and not anything to do with opt vs debug etc. What version
of scons do you have? ("scons -v") I don't see this problem with v0.96.92.

Steve
Sujay Phadke
2007-05-17 20:42:21 UTC
Permalink
ok thanks, that got solved. I am using scons script: v0.96.91.D001.
I just rebuilt the whole thing.

- Sujay

----- Original Message -----
From: "Steve Reinhardt" <***@eecs.umich.edu>
To: "M5 users mailing list" <m5-***@m5sim.org>
Sent: Thursday, May 17, 2007 3:09 PM
Subject: Re: [m5-users] compiling beta3
Post by Steve Reinhardt
Post by Sujay Phadke
Hello,
I just started using M5. I am trying to compile the beta3. It gives the
scons: Reading SConscript files ...
Checking for C header file Python.h... (cached) yes
Checking for main() in C library python2.5... (cached) yes
Checking for accept(0,0,0) in C++ library None... (cached) yes
Checking for zlibVersion() in C++ library z... (cached) yes
Checking for C header file fenv.h... (cached) yes
Building in /n/rtcl20/home/sphadke/research/m5/m5-2.0b3/build/ALPHA_SE
Options file
/n/rtcl20/home/sphadke/research/m5/m5-2.0b3/build/options/ALPHA_SE not
found,
using defaults in build_opts/ALPHA_SE
scons: done reading SConscript files.
scons: Building targets ...
It does run thru and build finally, but hy does it not find the options
file? Is that required?
It's just a standard notification the first time you build in a new
directory... it didn't find any saved build options from the last time you
built (since there was no last time), so it's initializing the saved
options with the default values. If this was actually an error it would
say "error" or something like that.
http://www.m5sim.org/wiki/index.php/Compiling_M5#Compiling
http://www.m5sim.org/wiki/index.php/SCons_build_system
Post by Sujay Phadke
Also, I cannot build anything other than the debug. If I try opt on
scons build/ALPHA_SE/m5.opt
scons: Reading SConscript files ...
Checking for C header file Python.h... (cached) yes
Checking for main() in C library python2.5... (cached) yes
Checking for accept(0,0,0) in C++ library None... (cached) yes
Checking for zlibVersion() in C++ library z... (cached) yes
Checking for C header file fenv.h... (cached) yes
Building in /n/rtcl20/home/sphadke/research/m5/m5-2.0b3/build/ALPHA_SE
Using saved options file
/n/rtcl20/home/sphadke/research/m5/m5-2.0b3/build/options/ALPHA_SE
scons: *** Error converting option: CPU_MODELS
Invalid value(s) for option: <built-in function all>
File "SConstruct", line 611, in <module>
It looks like it's having problems reloading the saved options... I'm
guessing this is just because it's the second time you've tried to build
something, and not anything to do with opt vs debug etc. What version of
scons do you have? ("scons -v") I don't see this problem with v0.96.92.
Steve
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Nathan Binkert
2007-05-17 22:45:09 UTC
Permalink
Post by Steve Reinhardt
It looks like it's having problems reloading the saved options... I'm
guessing this is just because it's the second time you've tried to build
something, and not anything to do with opt vs debug etc. What version of
scons do you have? ("scons -v") I don't see this problem with v0.96.92.
I saw this once, and had to change wherever it said:

CPU_MODELS = all

to say:

CPU_MODELS = 'all'


We don't actually write out the value all, so it does seem like a scons
bug, but I can't promise that.

Nate
Sujay Sunil Phadke
2007-05-18 17:23:51 UTC
Permalink
You're right that does solve the problem! I just changed the value in
build/options

- Sujay
Post by Nathan Binkert
Post by Steve Reinhardt
It looks like it's having problems reloading the saved options... I'm
guessing this is just because it's the second time you've tried to build
something, and not anything to do with opt vs debug etc. What version of
scons do you have? ("scons -v") I don't see this problem with v0.96.92.
CPU_MODELS = all
CPU_MODELS = 'all'
We don't actually write out the value all, so it does seem like a scons bug,
but I can't promise that.
Nate
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Ali Saidi
2007-05-17 03:48:02 UTC
Permalink
Post by Jiayuan
Thanks Gabe! So Alpha is the choice at this time.
But I'm still fuzzy on the CMP simulation with M5.
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
It is possible. If you look at our 00.hello-mp regression test you
can get an idea of how a CMP would be setup. However,
by default there isn't any sharing. Each core is executing a
different process.
Post by Jiayuan
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
adding more ops to the ISA, adding a load balancer unit to the
simulator
that creates threads (allocate stack size, set per-thread stack pointers,
passing thread contexts). Would you please give some hints on how to
implement these in M5?
This will be very difficult to implement in M5. You'll have to pretty
much re-implement the pthreads library as well as a process/context
switcher and a scheduler. Why not just run a full-system simulation
and use pthreads?
* New instructions can be implemented as pseudo ops: src/sim/
pseudo_inst.* and src/arch/alpha/isa/decoder.isa
* To add new syscalls have a look at src/arch/alpha/(linux|tru64)/*
and kern/(tru64|linux)/*
* Initial stacks and the like are created in src/sim/process.cc and
src/arch/alpha/process.cc
* We haven't implemented something like a scheduler, so there isn't a
place for you to look at source code, but to implement it well you'll
probably want some kind of interrupt to happen in the cpu's tick()
loop and you can go off and save one threads state and restore a
different ones. We do something like that for window traps on SPARC.
(src/arch/sparc/faults.cc|process.cc)
Post by Jiayuan
3. How Flexible is the memory system? In se.py, private L1 caches are
specified, and I saw in BaseCPU.py that a private L2 cache can also be
added, but what if I want to have private L1 caches for each core and a
shared L2 cache?
That would work fine as well, but with 2.0b3 you can only have one
level of coherence. By the time 2.0f is out that will be solved.
Post by Jiayuan
4. How fast is M5? How many instructions can M5 run in one second on
average?
It completely depends on your memory system configuration, how many
cpus you have and what kind of cpus you have as well as what hardware
you're running it on. 64bit x86 machine tend to be significantly
faster than 32bit ones.
Post by Jiayuan
5. Why the test case radix doesn't work under ALPHA_SE, and instead it
warn: loadGlobalSymbols: bad symbol header magic on
tests/test-progs/radix/bin/radix
warn: ignoring syscall sigprocmask(3, 18446744073709551615, ...)
warn: ignoring syscall sigprocmask(3, 0, ...)
warn: ignoring syscall sigaction(8, 4831387552, ...)
warn: ignoring syscall sigaction(11, 4831387552, ...)
warn: ignoring syscall sigaction(10, 4831387552, ...)
warn: ignoring syscall sigaction(4, 4831387552, ...)
warn: ignoring syscall sigaction(7, 4831387552, ...)
warn: ignoring syscall sigaction(6, 4831387552, ...)
warn: ignoring syscall sigaction(12, 4831387552, ...)
warn: ignoring syscall sigaction(5, 4831387552, ...)
warn: ignoring syscall sigaction(13, 4831387552, ...)
These warnings are normal. They are just informative, the benchmark
is running.

Ali
Post by Jiayuan
Thanks!
Jiayuan
-----Original Message-----
Sent: Tuesday, May 15, 2007 11:37 PM
To: M5 users mailing list; Jiayuan
Subject: Re: CMP simulation in SE mode + RE: [m5-users] question on test
code compilation
One thing I noticed is that you said you compiled your binaries on a
SunOS
machine. SPARC SE only supports Linux binaries at the moment, so you'll need
to
recompile. Also, SPARC support is not totally production ready
right now, so
you
could quite possibly run into problems which are not your fault. If you need
something that's very likely to work, I would recommend using
Alpha. If you
decide to use SPARC, please let us know of any bugs you might find and/or
fix.
Gabe
Post by Jiayuan
Thanks a lot Steve!
I am trying to model a CMP architecture. I think at this stage, I will not
model OS. I would prefer to run with syscall emulation mode. So I have two
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
adding
Post by Jiayuan
more ops to the ISA, adding a load balancer unit to the simulator that
creates threads (allocate stack size, set per-thread stack pointers,
passing
Post by Jiayuan
thread contexts). Would you please give some hints on how to
implement
these
Post by Jiayuan
in M5?
Thanks!
Jiayuan
-----Original Message-----
Behalf Of Steve Reinhardt
Sent: Tuesday, May 15, 2007 2:39 PM
To: M5 users mailing list
Subject: Re: [m5-users] question on test code compilation
M5 can run pthreads binaries in full-system mode, which means you're
restricted to Alpha for now.
http://www.m5sim.org/wiki/index.php/Using_linux-
dist_to_Create_Disk_Images_a
Post by Jiayuan
nd_Kernels_for_M5
Note that you just need to follow the first section (on building the
cross compiler); the other parts on building a new kernel are
unnecessary if you're just compiling new applications.
Steve
Post by Jiayuan Meng
Hi all,
I am a starter on M5, and I'm interested in simulating a
multithreaded
program on a CMP architecture. My question is, can M5 run programs
written with pthreads? what crosscompiler do you recommend to compile C
or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?
I tried to compile helloworld code on UltraSparc IIIi/SunOS using gcc
version 3.3.6. However, the sparc binary generates faults when the code
is run on M5. Would you please give me some hints?
Thanks!
Jiayuan
--------------------------------------------------------------------
----
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Jiayuan
2007-05-17 05:05:00 UTC
Permalink
Hi Ali,

Thank you so much for the helpful elaboration!

Some follow up questions:
Where can I find 00.hello-mp?

For simulating the multithreaded program, we actually want to test different
scheduling policies and load balance the workloads among cores. Using
Pthreads under FS mode might be a good option, is there a scheduler in FS
mode where I can implement different scheduling policies? If there isn't a
scheduler, what do I have to do to add one myself?

Thanks again!

Jiayuan
Post by Jiayuan
Thanks Gabe! So Alpha is the choice at this time.
But I'm still fuzzy on the CMP simulation with M5.
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
It is possible. If you look at our 00.hello-mp regression test you
can get an idea of how a CMP would be setup. However,
by default there isn't any sharing. Each core is executing a
different process.
Post by Jiayuan
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
adding more ops to the ISA, adding a load balancer unit to the
simulator
that creates threads (allocate stack size, set per-thread stack pointers,
passing thread contexts). Would you please give some hints on how to
implement these in M5?
This will be very difficult to implement in M5. You'll have to pretty
much re-implement the pthreads library as well as a process/context
switcher and a scheduler. Why not just run a full-system simulation
and use pthreads?
* New instructions can be implemented as pseudo ops: src/sim/
pseudo_inst.* and src/arch/alpha/isa/decoder.isa
* To add new syscalls have a look at src/arch/alpha/(linux|tru64)/*
and kern/(tru64|linux)/*
* Initial stacks and the like are created in src/sim/process.cc and
src/arch/alpha/process.cc
* We haven't implemented something like a scheduler, so there isn't a
place for you to look at source code, but to implement it well you'll
probably want some kind of interrupt to happen in the cpu's tick()
loop and you can go off and save one threads state and restore a
different ones. We do something like that for window traps on SPARC.
(src/arch/sparc/faults.cc|process.cc)
Post by Jiayuan
3. How Flexible is the memory system? In se.py, private L1 caches are
specified, and I saw in BaseCPU.py that a private L2 cache can also be
added, but what if I want to have private L1 caches for each core and a
shared L2 cache?
That would work fine as well, but with 2.0b3 you can only have one
level of coherence. By the time 2.0f is out that will be solved.
Post by Jiayuan
4. How fast is M5? How many instructions can M5 run in one second on
average?
It completely depends on your memory system configuration, how many
cpus you have and what kind of cpus you have as well as what hardware
you're running it on. 64bit x86 machine tend to be significantly
faster than 32bit ones.
Post by Jiayuan
5. Why the test case radix doesn't work under ALPHA_SE, and instead it
warn: loadGlobalSymbols: bad symbol header magic on
tests/test-progs/radix/bin/radix
warn: ignoring syscall sigprocmask(3, 18446744073709551615, ...)
warn: ignoring syscall sigprocmask(3, 0, ...)
warn: ignoring syscall sigaction(8, 4831387552, ...)
warn: ignoring syscall sigaction(11, 4831387552, ...)
warn: ignoring syscall sigaction(10, 4831387552, ...)
warn: ignoring syscall sigaction(4, 4831387552, ...)
warn: ignoring syscall sigaction(7, 4831387552, ...)
warn: ignoring syscall sigaction(6, 4831387552, ...)
warn: ignoring syscall sigaction(12, 4831387552, ...)
warn: ignoring syscall sigaction(5, 4831387552, ...)
warn: ignoring syscall sigaction(13, 4831387552, ...)
These warnings are normal. They are just informative, the benchmark
is running.

Ali
Post by Jiayuan
Thanks!
Jiayuan
-----Original Message-----
Sent: Tuesday, May 15, 2007 11:37 PM
To: M5 users mailing list; Jiayuan
Subject: Re: CMP simulation in SE mode + RE: [m5-users] question on test
code compilation
One thing I noticed is that you said you compiled your binaries on a
SunOS
machine. SPARC SE only supports Linux binaries at the moment, so you'll need
to
recompile. Also, SPARC support is not totally production ready
right now, so
you
could quite possibly run into problems which are not your fault. If you need
something that's very likely to work, I would recommend using
Alpha. If you
decide to use SPARC, please let us know of any bugs you might find and/or
fix.
Gabe
Post by Jiayuan
Thanks a lot Steve!
I am trying to model a CMP architecture. I think at this stage, I will not
model OS. I would prefer to run with syscall emulation mode. So I have two
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
adding
Post by Jiayuan
more ops to the ISA, adding a load balancer unit to the simulator that
creates threads (allocate stack size, set per-thread stack pointers,
passing
Post by Jiayuan
thread contexts). Would you please give some hints on how to
implement
these
Post by Jiayuan
in M5?
Thanks!
Jiayuan
-----Original Message-----
Behalf Of Steve Reinhardt
Sent: Tuesday, May 15, 2007 2:39 PM
To: M5 users mailing list
Subject: Re: [m5-users] question on test code compilation
M5 can run pthreads binaries in full-system mode, which means you're
restricted to Alpha for now.
http://www.m5sim.org/wiki/index.php/Using_linux-
dist_to_Create_Disk_Images_a
Post by Jiayuan
nd_Kernels_for_M5
Note that you just need to follow the first section (on building the
cross compiler); the other parts on building a new kernel are
unnecessary if you're just compiling new applications.
Steve
Post by Jiayuan Meng
Hi all,
I am a starter on M5, and I'm interested in simulating a
multithreaded
program on a CMP architecture. My question is, can M5 run programs
written with pthreads? what crosscompiler do you recommend to compile C
or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?
I tried to compile helloworld code on UltraSparc IIIi/SunOS using gcc
version 3.3.6. However, the sparc binary generates faults when the code
is run on M5. Would you please give me some hints?
Thanks!
Jiayuan
--------------------------------------------------------------------
----
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Ali Saidi
2007-05-17 13:21:03 UTC
Permalink
Post by Jiayuan
Hi Ali,
Thank you so much for the helpful elaboration!
Where can I find 00.hello-mp?
The test is in tests/quick/00.hello-mp/
Post by Jiayuan
For simulating the multithreaded program, we actually want to test different
scheduling policies and load balance the workloads among cores. Using
Pthreads under FS mode might be a good option, is there a scheduler in FS
mode where I can implement different scheduling policies? If there isn't a
scheduler, what do I have to do to add one myself?
The schedule in FS mode would be the normal Linux O(1) scheduler. If
you wanted to modify scheduling prorities you would need to modify
the scheduler in the Linux kernel (it's in sched.c).

Ali
Post by Jiayuan
Thanks again!
Jiayuan
Post by Jiayuan
Thanks Gabe! So Alpha is the choice at this time.
But I'm still fuzzy on the CMP simulation with M5.
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
It is possible. If you look at our 00.hello-mp regression test you
can get an idea of how a CMP would be setup. However,
by default there isn't any sharing. Each core is executing a
different process.
Post by Jiayuan
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
simulator. There might be other primitives as well. This may
adding more ops to the ISA, adding a load balancer unit to the
simulator
that creates threads (allocate stack size, set per-thread stack pointers,
passing thread contexts). Would you please give some hints on how to
implement these in M5?
This will be very difficult to implement in M5. You'll have to pretty
much re-implement the pthreads library as well as a process/context
switcher and a scheduler. Why not just run a full-system simulation
and use pthreads?
* New instructions can be implemented as pseudo ops: src/sim/
pseudo_inst.* and src/arch/alpha/isa/decoder.isa
* To add new syscalls have a look at src/arch/alpha/(linux|tru64)/*
and kern/(tru64|linux)/*
* Initial stacks and the like are created in src/sim/process.cc and
src/arch/alpha/process.cc
* We haven't implemented something like a scheduler, so there isn't a
place for you to look at source code, but to implement it well you'll
probably want some kind of interrupt to happen in the cpu's tick()
loop and you can go off and save one threads state and restore a
different ones. We do something like that for window traps on SPARC.
(src/arch/sparc/faults.cc|process.cc)
Post by Jiayuan
3. How Flexible is the memory system? In se.py, private L1 caches are
specified, and I saw in BaseCPU.py that a private L2 cache can also be
added, but what if I want to have private L1 caches for each core and a
shared L2 cache?
That would work fine as well, but with 2.0b3 you can only have one
level of coherence. By the time 2.0f is out that will be solved.
Post by Jiayuan
4. How fast is M5? How many instructions can M5 run in one second on
average?
It completely depends on your memory system configuration, how many
cpus you have and what kind of cpus you have as well as what hardware
you're running it on. 64bit x86 machine tend to be significantly
faster than 32bit ones.
Post by Jiayuan
5. Why the test case radix doesn't work under ALPHA_SE, and
instead it
warn: loadGlobalSymbols: bad symbol header magic on
tests/test-progs/radix/bin/radix
warn: ignoring syscall sigprocmask(3, 18446744073709551615, ...)
warn: ignoring syscall sigprocmask(3, 0, ...)
warn: ignoring syscall sigaction(8, 4831387552, ...)
warn: ignoring syscall sigaction(11, 4831387552, ...)
warn: ignoring syscall sigaction(10, 4831387552, ...)
warn: ignoring syscall sigaction(4, 4831387552, ...)
warn: ignoring syscall sigaction(7, 4831387552, ...)
warn: ignoring syscall sigaction(6, 4831387552, ...)
warn: ignoring syscall sigaction(12, 4831387552, ...)
warn: ignoring syscall sigaction(5, 4831387552, ...)
warn: ignoring syscall sigaction(13, 4831387552, ...)
These warnings are normal. They are just informative, the benchmark
is running.
Ali
Post by Jiayuan
Thanks!
Jiayuan
-----Original Message-----
Sent: Tuesday, May 15, 2007 11:37 PM
To: M5 users mailing list; Jiayuan
Subject: Re: CMP simulation in SE mode + RE: [m5-users] question on test
code compilation
One thing I noticed is that you said you compiled your binaries on a
SunOS
machine. SPARC SE only supports Linux binaries at the moment, so you'll need
to
recompile. Also, SPARC support is not totally production ready
right now, so
you
could quite possibly run into problems which are not your fault. If you need
something that's very likely to work, I would recommend using
Alpha. If you
decide to use SPARC, please let us know of any bugs you might find and/or
fix.
Gabe
Post by Jiayuan
Thanks a lot Steve!
I am trying to model a CMP architecture. I think at this stage, I will not
model OS. I would prefer to run with syscall emulation mode. So I have two
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
simulator. There might be other primitives as well. This may
adding
Post by Jiayuan
more ops to the ISA, adding a load balancer unit to the simulator that
creates threads (allocate stack size, set per-thread stack pointers,
passing
Post by Jiayuan
thread contexts). Would you please give some hints on how to
implement
these
Post by Jiayuan
in M5?
Thanks!
Jiayuan
-----Original Message-----
Behalf Of Steve Reinhardt
Sent: Tuesday, May 15, 2007 2:39 PM
To: M5 users mailing list
Subject: Re: [m5-users] question on test code compilation
M5 can run pthreads binaries in full-system mode, which means you're
restricted to Alpha for now.
http://www.m5sim.org/wiki/index.php/Using_linux-
dist_to_Create_Disk_Images_a
Post by Jiayuan
nd_Kernels_for_M5
Note that you just need to follow the first section (on building the
cross compiler); the other parts on building a new kernel are
unnecessary if you're just compiling new applications.
Steve
Post by Jiayuan Meng
Hi all,
I am a starter on M5, and I'm interested in simulating a
multithreaded
program on a CMP architecture. My question is, can M5 run programs
written with pthreads? what crosscompiler do you recommend to compile C
or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?
I tried to compile helloworld code on UltraSparc IIIi/SunOS using gcc
version 3.3.6. However, the sparc binary generates faults when the code
is run on M5. Would you please give me some hints?
Thanks!
Jiayuan
-------------------------------------------------------------------
-
----
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Jiayuan
2007-05-18 03:17:51 UTC
Permalink
Hi Ali and all,

Ron's Splash2 script runs smoothly and it looks beautiful! While digesting,
I have some more daily questions :)

1. When I am running several processes on several cores in SE mode, I found
that not all the processes are run to their end.

As described in 00.hello.mp, if all the four cores are running hello, the
simulator prints out four "hello world", as expected. But if I run three
hellos and one radix, the simulator prints out three "hello world" and
exits, the radix process never gets finished. How to fix this?

2. Is it possible to configure the interconnection among the cores? Say,
crossbar/mesh2D/torus ?

3. To add new instructions, I guess what you meant is to add a pseudoInst op
and then add the decoding method in decode.isa. However when reading
pseudoInst.*, I don't know how to use it and add new instructions. Do you
have an example? Also, if new instructions have to be encoded with bit
fields, it there a shortcut to know which kind of bit fields will not
conflict with the existing ones?

Thanks a lot!

Jiayuan


-----Original Message-----
From: m5-users-***@m5sim.org [mailto:m5-users-***@m5sim.org] On
Behalf Of Ali Saidi
Sent: Thursday, May 17, 2007 9:21 AM
To: M5 users mailing list
Subject: Re: [m5-users] CMP simulation in SE mode
Post by Jiayuan
Hi Ali,
Thank you so much for the helpful elaboration!
Where can I find 00.hello-mp?
The test is in tests/quick/00.hello-mp/
Post by Jiayuan
For simulating the multithreaded program, we actually want to test different
scheduling policies and load balance the workloads among cores. Using
Pthreads under FS mode might be a good option, is there a scheduler in FS
mode where I can implement different scheduling policies? If there isn't a
scheduler, what do I have to do to add one myself?
The schedule in FS mode would be the normal Linux O(1) scheduler. If
you wanted to modify scheduling prorities you would need to modify
the scheduler in the Linux kernel (it's in sched.c).

Ali
Post by Jiayuan
Thanks again!
Jiayuan
Post by Jiayuan
Thanks Gabe! So Alpha is the choice at this time.
But I'm still fuzzy on the CMP simulation with M5.
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
It is possible. If you look at our 00.hello-mp regression test you
can get an idea of how a CMP would be setup. However,
by default there isn't any sharing. Each core is executing a
different process.
Post by Jiayuan
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
simulator. There might be other primitives as well. This may
adding more ops to the ISA, adding a load balancer unit to the
simulator
that creates threads (allocate stack size, set per-thread stack pointers,
passing thread contexts). Would you please give some hints on how to
implement these in M5?
This will be very difficult to implement in M5. You'll have to pretty
much re-implement the pthreads library as well as a process/context
switcher and a scheduler. Why not just run a full-system simulation
and use pthreads?
* New instructions can be implemented as pseudo ops: src/sim/
pseudo_inst.* and src/arch/alpha/isa/decoder.isa
* To add new syscalls have a look at src/arch/alpha/(linux|tru64)/*
and kern/(tru64|linux)/*
* Initial stacks and the like are created in src/sim/process.cc and
src/arch/alpha/process.cc
* We haven't implemented something like a scheduler, so there isn't a
place for you to look at source code, but to implement it well you'll
probably want some kind of interrupt to happen in the cpu's tick()
loop and you can go off and save one threads state and restore a
different ones. We do something like that for window traps on SPARC.
(src/arch/sparc/faults.cc|process.cc)
Post by Jiayuan
3. How Flexible is the memory system? In se.py, private L1 caches are
specified, and I saw in BaseCPU.py that a private L2 cache can also be
added, but what if I want to have private L1 caches for each core and a
shared L2 cache?
That would work fine as well, but with 2.0b3 you can only have one
level of coherence. By the time 2.0f is out that will be solved.
Post by Jiayuan
4. How fast is M5? How many instructions can M5 run in one second on
average?
It completely depends on your memory system configuration, how many
cpus you have and what kind of cpus you have as well as what hardware
you're running it on. 64bit x86 machine tend to be significantly
faster than 32bit ones.
Post by Jiayuan
5. Why the test case radix doesn't work under ALPHA_SE, and
instead it
warn: loadGlobalSymbols: bad symbol header magic on
tests/test-progs/radix/bin/radix
warn: ignoring syscall sigprocmask(3, 18446744073709551615, ...)
warn: ignoring syscall sigprocmask(3, 0, ...)
warn: ignoring syscall sigaction(8, 4831387552, ...)
warn: ignoring syscall sigaction(11, 4831387552, ...)
warn: ignoring syscall sigaction(10, 4831387552, ...)
warn: ignoring syscall sigaction(4, 4831387552, ...)
warn: ignoring syscall sigaction(7, 4831387552, ...)
warn: ignoring syscall sigaction(6, 4831387552, ...)
warn: ignoring syscall sigaction(12, 4831387552, ...)
warn: ignoring syscall sigaction(5, 4831387552, ...)
warn: ignoring syscall sigaction(13, 4831387552, ...)
These warnings are normal. They are just informative, the benchmark
is running.
Ali
Post by Jiayuan
Thanks!
Jiayuan
-----Original Message-----
Sent: Tuesday, May 15, 2007 11:37 PM
To: M5 users mailing list; Jiayuan
Subject: Re: CMP simulation in SE mode + RE: [m5-users] question on test
code compilation
One thing I noticed is that you said you compiled your binaries on a
SunOS
machine. SPARC SE only supports Linux binaries at the moment, so you'll need
to
recompile. Also, SPARC support is not totally production ready
right now, so
you
could quite possibly run into problems which are not your fault. If you need
something that's very likely to work, I would recommend using
Alpha. If you
decide to use SPARC, please let us know of any bugs you might find and/or
fix.
Gabe
Post by Jiayuan
Thanks a lot Steve!
I am trying to model a CMP architecture. I think at this stage, I will not
model OS. I would prefer to run with syscall emulation mode. So I have two
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
simulator. There might be other primitives as well. This may
adding
Post by Jiayuan
more ops to the ISA, adding a load balancer unit to the simulator that
creates threads (allocate stack size, set per-thread stack pointers,
passing
Post by Jiayuan
thread contexts). Would you please give some hints on how to
implement
these
Post by Jiayuan
in M5?
Thanks!
Jiayuan
-----Original Message-----
Behalf Of Steve Reinhardt
Sent: Tuesday, May 15, 2007 2:39 PM
To: M5 users mailing list
Subject: Re: [m5-users] question on test code compilation
M5 can run pthreads binaries in full-system mode, which means you're
restricted to Alpha for now.
http://www.m5sim.org/wiki/index.php/Using_linux-
dist_to_Create_Disk_Images_a
Post by Jiayuan
nd_Kernels_for_M5
Note that you just need to follow the first section (on building the
cross compiler); the other parts on building a new kernel are
unnecessary if you're just compiling new applications.
Steve
Post by Jiayuan Meng
Hi all,
I am a starter on M5, and I'm interested in simulating a
multithreaded
program on a CMP architecture. My question is, can M5 run programs
written with pthreads? what crosscompiler do you recommend to compile C
or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?
I tried to compile helloworld code on UltraSparc IIIi/SunOS using gcc
version 3.3.6. However, the sparc binary generates faults when the code
is run on M5. Would you please give me some hints?
Thanks!
Jiayuan
-------------------------------------------------------------------
-
----
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Ali Saidi
2007-05-18 03:49:18 UTC
Permalink
Post by Jiayuan
Hi Ali and all,
Ron's Splash2 script runs smoothly and it looks beautiful! While digesting,
I have some more daily questions :)
1. When I am running several processes on several cores in SE mode, I found
that not all the processes are run to their end.
As described in 00.hello.mp, if all the four cores are running
hello, the
simulator prints out four "hello world", as expected. But if I run three
hellos and one radix, the simulator prints out three "hello world" and
exits, the radix process never gets finished. How to fix this?
As soon as one process finishes all the cores exit. It's rare that
you'll be running any real workload to completion inside M5, so that
is the default behavior. If you want to change it you'll probably
need to change how exitFunc() works in pseduo_inst.cc to make sure
that all processes have called exit.
Post by Jiayuan
2. Is it possible to configure the interconnection among the cores? Say,
crossbar/mesh2D/torus ?
Technically it is, however we don't have any models for them. If you
decide to create one please send us patches for your changes.
Post by Jiayuan
3. To add new instructions, I guess what you meant is to add a
pseudoInst op
and then add the decoding method in decode.isa. However when reading
pseudoInst.*, I don't know how to use it and add new instructions. Do you
have an example? Also, if new instructions have to be encoded with bit
fields, it there a shortcut to know which kind of bit fields will not
conflict with the existing ones?
If you search for the name M5FUNC in decoder.isa you'll see how we've
done it. There is some space available where those instructions are
encoded. Off the top of my head I don't know where else there are
available opcodes in the Alpha ISA. You should read the pages on the
instruction set description in the M5 documentation for more info.

Ali
Post by Jiayuan
-----Original Message-----
Behalf Of Ali Saidi
Sent: Thursday, May 17, 2007 9:21 AM
To: M5 users mailing list
Subject: Re: [m5-users] CMP simulation in SE mode
Post by Jiayuan
Hi Ali,
Thank you so much for the helpful elaboration!
Where can I find 00.hello-mp?
The test is in tests/quick/00.hello-mp/
Post by Jiayuan
For simulating the multithreaded program, we actually want to test different
scheduling policies and load balance the workloads among cores. Using
Pthreads under FS mode might be a good option, is there a scheduler in FS
mode where I can implement different scheduling policies? If there isn't a
scheduler, what do I have to do to add one myself?
The schedule in FS mode would be the normal Linux O(1) scheduler. If
you wanted to modify scheduling prorities you would need to modify
the scheduler in the Linux kernel (it's in sched.c).
Ali
Post by Jiayuan
Thanks again!
Jiayuan
Post by Jiayuan
Thanks Gabe! So Alpha is the choice at this time.
But I'm still fuzzy on the CMP simulation with M5.
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
It is possible. If you look at our 00.hello-mp regression test you
can get an idea of how a CMP would be setup. However,
by default there isn't any sharing. Each core is executing a
different process.
Post by Jiayuan
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
simulator. There might be other primitives as well. This may
adding more ops to the ISA, adding a load balancer unit to the
simulator
that creates threads (allocate stack size, set per-thread stack pointers,
passing thread contexts). Would you please give some hints on how to
implement these in M5?
This will be very difficult to implement in M5. You'll have to pretty
much re-implement the pthreads library as well as a process/context
switcher and a scheduler. Why not just run a full-system simulation
and use pthreads?
* New instructions can be implemented as pseudo ops: src/sim/
pseudo_inst.* and src/arch/alpha/isa/decoder.isa
* To add new syscalls have a look at src/arch/alpha/(linux|tru64)/*
and kern/(tru64|linux)/*
* Initial stacks and the like are created in src/sim/process.cc and
src/arch/alpha/process.cc
* We haven't implemented something like a scheduler, so there isn't a
place for you to look at source code, but to implement it well you'll
probably want some kind of interrupt to happen in the cpu's tick()
loop and you can go off and save one threads state and restore a
different ones. We do something like that for window traps on SPARC.
(src/arch/sparc/faults.cc|process.cc)
Post by Jiayuan
3. How Flexible is the memory system? In se.py, private L1 caches are
specified, and I saw in BaseCPU.py that a private L2 cache can also be
added, but what if I want to have private L1 caches for each core and a
shared L2 cache?
That would work fine as well, but with 2.0b3 you can only have one
level of coherence. By the time 2.0f is out that will be solved.
Post by Jiayuan
4. How fast is M5? How many instructions can M5 run in one
second on
average?
It completely depends on your memory system configuration, how many
cpus you have and what kind of cpus you have as well as what hardware
you're running it on. 64bit x86 machine tend to be significantly
faster than 32bit ones.
Post by Jiayuan
5. Why the test case radix doesn't work under ALPHA_SE, and
instead it
warn: loadGlobalSymbols: bad symbol header magic on
tests/test-progs/radix/bin/radix
warn: ignoring syscall sigprocmask(3, 18446744073709551615, ...)
warn: ignoring syscall sigprocmask(3, 0, ...)
warn: ignoring syscall sigaction(8, 4831387552, ...)
warn: ignoring syscall sigaction(11, 4831387552, ...)
warn: ignoring syscall sigaction(10, 4831387552, ...)
warn: ignoring syscall sigaction(4, 4831387552, ...)
warn: ignoring syscall sigaction(7, 4831387552, ...)
warn: ignoring syscall sigaction(6, 4831387552, ...)
warn: ignoring syscall sigaction(12, 4831387552, ...)
warn: ignoring syscall sigaction(5, 4831387552, ...)
warn: ignoring syscall sigaction(13, 4831387552, ...)
These warnings are normal. They are just informative, the benchmark
is running.
Ali
Post by Jiayuan
Thanks!
Jiayuan
-----Original Message-----
Sent: Tuesday, May 15, 2007 11:37 PM
To: M5 users mailing list; Jiayuan
Subject: Re: CMP simulation in SE mode + RE: [m5-users] question on test
code compilation
One thing I noticed is that you said you compiled your binaries on a
SunOS
machine. SPARC SE only supports Linux binaries at the moment, so you'll need
to
recompile. Also, SPARC support is not totally production ready
right now, so
you
could quite possibly run into problems which are not your fault. If you need
something that's very likely to work, I would recommend using
Alpha. If you
decide to use SPARC, please let us know of any bugs you might find and/or
fix.
Gabe
Post by Jiayuan
Thanks a lot Steve!
I am trying to model a CMP architecture. I think at this stage, I will not
model OS. I would prefer to run with syscall emulation mode. So I have two
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
simulator. There might be other primitives as well. This may
adding
Post by Jiayuan
more ops to the ISA, adding a load balancer unit to the simulator that
creates threads (allocate stack size, set per-thread stack
pointers,
passing
Post by Jiayuan
thread contexts). Would you please give some hints on how to
implement
these
Post by Jiayuan
in M5?
Thanks!
Jiayuan
-----Original Message-----
Behalf Of Steve Reinhardt
Sent: Tuesday, May 15, 2007 2:39 PM
To: M5 users mailing list
Subject: Re: [m5-users] question on test code compilation
M5 can run pthreads binaries in full-system mode, which means you're
restricted to Alpha for now.
http://www.m5sim.org/wiki/index.php/Using_linux-
dist_to_Create_Disk_Images_a
Post by Jiayuan
nd_Kernels_for_M5
Note that you just need to follow the first section (on building the
cross compiler); the other parts on building a new kernel are
unnecessary if you're just compiling new applications.
Steve
Post by Jiayuan Meng
Hi all,
I am a starter on M5, and I'm interested in simulating a
multithreaded
program on a CMP architecture. My question is, can M5 run programs
written with pthreads? what crosscompiler do you recommend to compile C
or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?
I tried to compile helloworld code on UltraSparc IIIi/SunOS using gcc
version 3.3.6. However, the sparc binary generates faults when the code
is run on M5. Would you please give me some hints?
Thanks!
Jiayuan
------------------------------------------------------------------
-
-
----
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Jiayuan
2007-05-18 16:56:53 UTC
Permalink
Thanks Steve and Ali! Time to digest :)



-----Original Message-----
From: m5-users-***@m5sim.org [mailto:m5-users-***@m5sim.org] On
Behalf Of Ali Saidi
Sent: Thursday, May 17, 2007 11:49 PM
To: M5 users mailing list
Subject: Re: [m5-users] processes on CMP && interconnection && new
instructions
Post by Jiayuan
Hi Ali and all,
Ron's Splash2 script runs smoothly and it looks beautiful! While digesting,
I have some more daily questions :)
1. When I am running several processes on several cores in SE mode, I found
that not all the processes are run to their end.
As described in 00.hello.mp, if all the four cores are running
hello, the
simulator prints out four "hello world", as expected. But if I run three
hellos and one radix, the simulator prints out three "hello world" and
exits, the radix process never gets finished. How to fix this?
As soon as one process finishes all the cores exit. It's rare that
you'll be running any real workload to completion inside M5, so that
is the default behavior. If you want to change it you'll probably
need to change how exitFunc() works in pseduo_inst.cc to make sure
that all processes have called exit.
Post by Jiayuan
2. Is it possible to configure the interconnection among the cores? Say,
crossbar/mesh2D/torus ?
Technically it is, however we don't have any models for them. If you
decide to create one please send us patches for your changes.
Post by Jiayuan
3. To add new instructions, I guess what you meant is to add a
pseudoInst op
and then add the decoding method in decode.isa. However when reading
pseudoInst.*, I don't know how to use it and add new instructions. Do you
have an example? Also, if new instructions have to be encoded with bit
fields, it there a shortcut to know which kind of bit fields will not
conflict with the existing ones?
If you search for the name M5FUNC in decoder.isa you'll see how we've
done it. There is some space available where those instructions are
encoded. Off the top of my head I don't know where else there are
available opcodes in the Alpha ISA. You should read the pages on the
instruction set description in the M5 documentation for more info.

Ali
Post by Jiayuan
-----Original Message-----
Behalf Of Ali Saidi
Sent: Thursday, May 17, 2007 9:21 AM
To: M5 users mailing list
Subject: Re: [m5-users] CMP simulation in SE mode
Post by Jiayuan
Hi Ali,
Thank you so much for the helpful elaboration!
Where can I find 00.hello-mp?
The test is in tests/quick/00.hello-mp/
Post by Jiayuan
For simulating the multithreaded program, we actually want to test different
scheduling policies and load balance the workloads among cores. Using
Pthreads under FS mode might be a good option, is there a scheduler in FS
mode where I can implement different scheduling policies? If there isn't a
scheduler, what do I have to do to add one myself?
The schedule in FS mode would be the normal Linux O(1) scheduler. If
you wanted to modify scheduling prorities you would need to modify
the scheduler in the Linux kernel (it's in sched.c).
Ali
Post by Jiayuan
Thanks again!
Jiayuan
Post by Jiayuan
Thanks Gabe! So Alpha is the choice at this time.
But I'm still fuzzy on the CMP simulation with M5.
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
It is possible. If you look at our 00.hello-mp regression test you
can get an idea of how a CMP would be setup. However,
by default there isn't any sharing. Each core is executing a
different process.
Post by Jiayuan
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
simulator. There might be other primitives as well. This may
adding more ops to the ISA, adding a load balancer unit to the
simulator
that creates threads (allocate stack size, set per-thread stack pointers,
passing thread contexts). Would you please give some hints on how to
implement these in M5?
This will be very difficult to implement in M5. You'll have to pretty
much re-implement the pthreads library as well as a process/context
switcher and a scheduler. Why not just run a full-system simulation
and use pthreads?
* New instructions can be implemented as pseudo ops: src/sim/
pseudo_inst.* and src/arch/alpha/isa/decoder.isa
* To add new syscalls have a look at src/arch/alpha/(linux|tru64)/*
and kern/(tru64|linux)/*
* Initial stacks and the like are created in src/sim/process.cc and
src/arch/alpha/process.cc
* We haven't implemented something like a scheduler, so there isn't a
place for you to look at source code, but to implement it well you'll
probably want some kind of interrupt to happen in the cpu's tick()
loop and you can go off and save one threads state and restore a
different ones. We do something like that for window traps on SPARC.
(src/arch/sparc/faults.cc|process.cc)
Post by Jiayuan
3. How Flexible is the memory system? In se.py, private L1 caches are
specified, and I saw in BaseCPU.py that a private L2 cache can also be
added, but what if I want to have private L1 caches for each core and a
shared L2 cache?
That would work fine as well, but with 2.0b3 you can only have one
level of coherence. By the time 2.0f is out that will be solved.
Post by Jiayuan
4. How fast is M5? How many instructions can M5 run in one
second on
average?
It completely depends on your memory system configuration, how many
cpus you have and what kind of cpus you have as well as what hardware
you're running it on. 64bit x86 machine tend to be significantly
faster than 32bit ones.
Post by Jiayuan
5. Why the test case radix doesn't work under ALPHA_SE, and
instead it
warn: loadGlobalSymbols: bad symbol header magic on
tests/test-progs/radix/bin/radix
warn: ignoring syscall sigprocmask(3, 18446744073709551615, ...)
warn: ignoring syscall sigprocmask(3, 0, ...)
warn: ignoring syscall sigaction(8, 4831387552, ...)
warn: ignoring syscall sigaction(11, 4831387552, ...)
warn: ignoring syscall sigaction(10, 4831387552, ...)
warn: ignoring syscall sigaction(4, 4831387552, ...)
warn: ignoring syscall sigaction(7, 4831387552, ...)
warn: ignoring syscall sigaction(6, 4831387552, ...)
warn: ignoring syscall sigaction(12, 4831387552, ...)
warn: ignoring syscall sigaction(5, 4831387552, ...)
warn: ignoring syscall sigaction(13, 4831387552, ...)
These warnings are normal. They are just informative, the benchmark
is running.
Ali
Post by Jiayuan
Thanks!
Jiayuan
-----Original Message-----
Sent: Tuesday, May 15, 2007 11:37 PM
To: M5 users mailing list; Jiayuan
Subject: Re: CMP simulation in SE mode + RE: [m5-users] question on test
code compilation
One thing I noticed is that you said you compiled your binaries on a
SunOS
machine. SPARC SE only supports Linux binaries at the moment, so you'll need
to
recompile. Also, SPARC support is not totally production ready
right now, so
you
could quite possibly run into problems which are not your fault. If you need
something that's very likely to work, I would recommend using
Alpha. If you
decide to use SPARC, please let us know of any bugs you might find and/or
fix.
Gabe
Post by Jiayuan
Thanks a lot Steve!
I am trying to model a CMP architecture. I think at this stage, I will not
model OS. I would prefer to run with syscall emulation mode. So I have two
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
simulator. There might be other primitives as well. This may
adding
Post by Jiayuan
more ops to the ISA, adding a load balancer unit to the simulator that
creates threads (allocate stack size, set per-thread stack
pointers,
passing
Post by Jiayuan
thread contexts). Would you please give some hints on how to
implement
these
Post by Jiayuan
in M5?
Thanks!
Jiayuan
-----Original Message-----
Behalf Of Steve Reinhardt
Sent: Tuesday, May 15, 2007 2:39 PM
To: M5 users mailing list
Subject: Re: [m5-users] question on test code compilation
M5 can run pthreads binaries in full-system mode, which means you're
restricted to Alpha for now.
http://www.m5sim.org/wiki/index.php/Using_linux-
dist_to_Create_Disk_Images_a
Post by Jiayuan
nd_Kernels_for_M5
Note that you just need to follow the first section (on building the
cross compiler); the other parts on building a new kernel are
unnecessary if you're just compiling new applications.
Steve
Post by Jiayuan Meng
Hi all,
I am a starter on M5, and I'm interested in simulating a
multithreaded
program on a CMP architecture. My question is, can M5 run programs
written with pthreads? what crosscompiler do you recommend to compile C
or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?
I tried to compile helloworld code on UltraSparc IIIi/SunOS using gcc
version 3.3.6. However, the sparc binary generates faults when the code
is run on M5. Would you please give me some hints?
Thanks!
Jiayuan
------------------------------------------------------------------
-
-
----
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Steve Reinhardt
2007-05-18 03:50:39 UTC
Permalink
Post by Jiayuan
Hi Ali and all,
Ron's Splash2 script runs smoothly and it looks beautiful! While digesting,
I have some more daily questions :)
1. When I am running several processes on several cores in SE mode, I found
that not all the processes are run to their end.
As described in 00.hello.mp, if all the four cores are running hello, the
simulator prints out four "hello world", as expected. But if I run three
hellos and one radix, the simulator prints out three "hello world" and
exits, the radix process never gets finished. How to fix this?
See exitFunc() in src/sim/syscall_emul.cc. By default the simulation
terminates when the first program calls exit(), since if you're
measuring a multiprogrammed workload it's not clear that you want to
include the time when not all of the applications are running in your
performance measurements. The short answer is that you don't want to
call exitSimLoop() right away there, you want to wait until the Nth time
it's called (where N is the number of originally running processes).
Offhand I don't know of an easy way to figure out what the value of N is
though. In the short term you could hard-wire it to 4 or whatever
you're using.
Post by Jiayuan
2. Is it possible to configure the interconnection among the cores? Say,
crossbar/mesh2D/torus ?
Yes, the caches just use ports to send packets around, an interface (new
in v2) which we designed specifically to allow you to pull out the bus
and put in a different interconnect. However the bus is all we have, so
you would have to write the simulation model for the other interconnect
yourself. Also the snooping coherence protocol is the only one we have
right now so you might have to develop a new protocol too, though if you
only run multiprogrammed workloads that don't share data then you could
get away without that.
Post by Jiayuan
3. To add new instructions, I guess what you meant is to add a pseudoInst op
and then add the decoding method in decode.isa. However when reading
pseudoInst.*, I don't know how to use it and add new instructions. Do you
have an example? Also, if new instructions have to be encoded with bit
fields, it there a shortcut to know which kind of bit fields will not
conflict with the existing ones?
It's not very hard, but I've never done it myself, so I can't give you
the specifics off the top of my head. I would think that you could use
the existing pseudo instructions as examples/templates for adding your
own. Look for M5FUNC in src/arch/alpha/isa/decoder.isa.

Steve
Post by Jiayuan
Thanks a lot!
Jiayuan
-----Original Message-----
Behalf Of Ali Saidi
Sent: Thursday, May 17, 2007 9:21 AM
To: M5 users mailing list
Subject: Re: [m5-users] CMP simulation in SE mode
Post by Jiayuan
Hi Ali,
Thank you so much for the helpful elaboration!
Where can I find 00.hello-mp?
The test is in tests/quick/00.hello-mp/
Post by Jiayuan
For simulating the multithreaded program, we actually want to test different
scheduling policies and load balance the workloads among cores. Using
Pthreads under FS mode might be a good option, is there a scheduler in FS
mode where I can implement different scheduling policies? If there isn't a
scheduler, what do I have to do to add one myself?
The schedule in FS mode would be the normal Linux O(1) scheduler. If
you wanted to modify scheduling prorities you would need to modify
the scheduler in the Linux kernel (it's in sched.c).
Ali
Post by Jiayuan
Thanks again!
Jiayuan
Post by Jiayuan
Thanks Gabe! So Alpha is the choice at this time.
But I'm still fuzzy on the CMP simulation with M5.
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
It is possible. If you look at our 00.hello-mp regression test you
can get an idea of how a CMP would be setup. However,
by default there isn't any sharing. Each core is executing a
different process.
Post by Jiayuan
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
simulator. There might be other primitives as well. This may
adding more ops to the ISA, adding a load balancer unit to the
simulator
that creates threads (allocate stack size, set per-thread stack pointers,
passing thread contexts). Would you please give some hints on how to
implement these in M5?
This will be very difficult to implement in M5. You'll have to pretty
much re-implement the pthreads library as well as a process/context
switcher and a scheduler. Why not just run a full-system simulation
and use pthreads?
* New instructions can be implemented as pseudo ops: src/sim/
pseudo_inst.* and src/arch/alpha/isa/decoder.isa
* To add new syscalls have a look at src/arch/alpha/(linux|tru64)/*
and kern/(tru64|linux)/*
* Initial stacks and the like are created in src/sim/process.cc and
src/arch/alpha/process.cc
* We haven't implemented something like a scheduler, so there isn't a
place for you to look at source code, but to implement it well you'll
probably want some kind of interrupt to happen in the cpu's tick()
loop and you can go off and save one threads state and restore a
different ones. We do something like that for window traps on SPARC.
(src/arch/sparc/faults.cc|process.cc)
Post by Jiayuan
3. How Flexible is the memory system? In se.py, private L1 caches are
specified, and I saw in BaseCPU.py that a private L2 cache can also be
added, but what if I want to have private L1 caches for each core and a
shared L2 cache?
That would work fine as well, but with 2.0b3 you can only have one
level of coherence. By the time 2.0f is out that will be solved.
Post by Jiayuan
4. How fast is M5? How many instructions can M5 run in one second on
average?
It completely depends on your memory system configuration, how many
cpus you have and what kind of cpus you have as well as what hardware
you're running it on. 64bit x86 machine tend to be significantly
faster than 32bit ones.
Post by Jiayuan
5. Why the test case radix doesn't work under ALPHA_SE, and
instead it
warn: loadGlobalSymbols: bad symbol header magic on
tests/test-progs/radix/bin/radix
warn: ignoring syscall sigprocmask(3, 18446744073709551615, ...)
warn: ignoring syscall sigprocmask(3, 0, ...)
warn: ignoring syscall sigaction(8, 4831387552, ...)
warn: ignoring syscall sigaction(11, 4831387552, ...)
warn: ignoring syscall sigaction(10, 4831387552, ...)
warn: ignoring syscall sigaction(4, 4831387552, ...)
warn: ignoring syscall sigaction(7, 4831387552, ...)
warn: ignoring syscall sigaction(6, 4831387552, ...)
warn: ignoring syscall sigaction(12, 4831387552, ...)
warn: ignoring syscall sigaction(5, 4831387552, ...)
warn: ignoring syscall sigaction(13, 4831387552, ...)
These warnings are normal. They are just informative, the benchmark
is running.
Ali
Post by Jiayuan
Thanks!
Jiayuan
-----Original Message-----
Sent: Tuesday, May 15, 2007 11:37 PM
To: M5 users mailing list; Jiayuan
Subject: Re: CMP simulation in SE mode + RE: [m5-users] question on test
code compilation
One thing I noticed is that you said you compiled your binaries on a
SunOS
machine. SPARC SE only supports Linux binaries at the moment, so you'll need
to
recompile. Also, SPARC support is not totally production ready
right now, so
you
could quite possibly run into problems which are not your fault. If you need
something that's very likely to work, I would recommend using
Alpha. If you
decide to use SPARC, please let us know of any bugs you might find and/or
fix.
Gabe
Post by Jiayuan
Thanks a lot Steve!
I am trying to model a CMP architecture. I think at this stage, I will not
model OS. I would prefer to run with syscall emulation mode. So I have two
1. is it possible to simulate a CMP under SE mode? If so, do you have any
example scripts on configuring the CMP architecture? (in configs/
example,
se.py has only one SimpleCPU configured)
2. Since I have to run threads on this configuration with SE mode, I will
need to implement some thread creation/termination primitives in the
simulator. There might be other primitives as well. This may
adding
Post by Jiayuan
more ops to the ISA, adding a load balancer unit to the simulator that
creates threads (allocate stack size, set per-thread stack pointers,
passing
Post by Jiayuan
thread contexts). Would you please give some hints on how to
implement
these
Post by Jiayuan
in M5?
Thanks!
Jiayuan
-----Original Message-----
Behalf Of Steve Reinhardt
Sent: Tuesday, May 15, 2007 2:39 PM
To: M5 users mailing list
Subject: Re: [m5-users] question on test code compilation
M5 can run pthreads binaries in full-system mode, which means you're
restricted to Alpha for now.
http://www.m5sim.org/wiki/index.php/Using_linux-
dist_to_Create_Disk_Images_a
Post by Jiayuan
nd_Kernels_for_M5
Note that you just need to follow the first section (on building the
cross compiler); the other parts on building a new kernel are
unnecessary if you're just compiling new applications.
Steve
Post by Jiayuan Meng
Hi all,
I am a starter on M5, and I'm interested in simulating a
multithreaded
program on a CMP architecture. My question is, can M5 run programs
written with pthreads? what crosscompiler do you recommend to compile C
or C++ code on a x86 host to SPARC/ALPHA binaries that can be run on M5?
I tried to compile helloworld code on UltraSparc IIIi/SunOS using gcc
version 3.3.6. However, the sparc binary generates faults when the code
is run on M5. Would you please give me some hints?
Thanks!
Jiayuan
-------------------------------------------------------------------
-
----
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
Continue reading on narkive:
Loading...