Thanks for your comment Wei.
I have been thinking about how to simulate the bank contention or obstruction. I have to do that only when the LLC is written, in read cases it is only necessary to check if the bank is free. I think I can do that with the methods: recordRequestType(CacheRequestType requestType, Addr addr) and checkResourceAvailable(CacheResourceType res, Addr addr), I will insert that methods in the protocol definition, in case of Bank busy z-stall will be generated and another event into the queue will be processed for use the clock cycle doing something.
Thanks
Rodrigo.
> Date: Fri, 16 Oct 2015 14:01:48 -0500
> From: ***@louisiana.edu
> To: gem5-***@gem5.org
> Subject: Re: [gem5-users] Different Cache R/W Latency
>
> Somehow I come up an idea but might be stupid.
>
> Suppose you have a write event issued at curTick 1, your STT has longer latency than usual case, say 200 cycles.
> You can mark the current access curTick, and if next request is within curTick()+200, you don't return
> data.
>
> In this case you might also need to change protocol.
>
> Tanks,
> Wei
> ----- Original Message -----
> From: "Rodrigo Reynolds Ramírez" <***@hotmail.com>
> To: "gem5-users" <gem5-***@gem5.org>
> Sent: Friday, October 16, 2015 12:24:55 PM
> Subject: Re: [gem5-users] Different Cache R/W Latency
>
> Thanks Way,
>
> Analyzing a typical waveform chart from a cache access I know I need to change two latencies, the access latency and the latency I need to wait for send new petition.
>
> In a normal cache Read and Write latencies are the same, and I have to wait only one cycle before send a new petition to the cache, it does not matter is the access takes 2 or 20 cycles, I just need to wait 1 cycle before I can send a new petition. All the access path it is supposed to be pipelined.
>
> The problem is when Read and Write latencies are different (W>R) after a write I need to wait some cycles before I can send a new petition, the bank is blocked for a number of cycles after a write.
>
> I thought I could simulate that with the checkResourceAvailable functions. I am not sure if when I change the action latency I am changing just the access latency or both. Thanks.
>
> Best Regards
> Rodrigo
>
>
> > Date: Thu, 15 Oct 2015 16:29:35 -0500
> > From: ***@louisiana.edu
> > To: gem5-***@gem5.org
> > Subject: Re: [gem5-users] Different Cache R/W Latency
> >
> > Hi Rodrigo,
> >
> > You might need to take a look at some protocol event, assuming L2 is your LLC:
> > in src/mem/protocol/MESI_Two_Level-L2cache.sm:
> >
> > action(ds_sendSharedDataToRequestor, "ds", desc="Send data from cache to reqeustor") {
> > peek(L1RequestL2Network_in, RequestMsg) {
> > enqueue(responseL2Network_out, ResponseMsg, l2_response_latency) {//l2_response_latency is what you might need to change
> > ...
> > }
> > }
> > }
> >
> > A naive way is, if multiple latency values need to be set, write some if-else words to implement.
> >
> > Thanks,
> > Wei
> > ----- Original Message -----
> > From: "Rodrigo Reynolds Ramírez" <***@hotmail.com>
> > To: "gem5-users" <gem5-***@gem5.org>
> > Sent: Thursday, October 15, 2015 12:52:27 PM
> > Subject: Re: [gem5-users] Different Cache R/W Latency
> >
> > Thanks Cong,
> >
> > I will check the python scripts you say, I think the file I have to modify is src/mem/slicc/symbols/StateMachine.py it is the only file I have found that uses the checkResourceAvailable functions.
> >
> > I though I have to modify the slicc files or add an option to scons to enable the checkResourceAvailable functions, something like the SLICC_HTML option for generate the HTML state machine files.
> >
> > Best Regards,
> > Rodrigo
> >
> >
> > From: ***@gmail.com
> > Date: Thu, 15 Oct 2015 11:36:10 -0500
> > To: gem5-***@gem5.org
> > Subject: Re: [gem5-users] Different Cache R/W Latency
> >
> > Hi Rodrigo,
> >
> > In Ruby, all the bank availability utilities are never used. You need to change the ruby generation engine (a set of python files those translate slicc files to cpp files) to enable that checkResourceAvailable function or it will never get translated into the cpp files.
> >
> > Regards,
> > Cong
> >
> > On Thu, Oct 15, 2015 at 11:19 AM, Rodrigo Reynolds Ramírez < ***@hotmail.com > wrote:
> >
> >
> >
> > I have a new question regarding latencies in Ruby, I am wonder that the methods associated to check bank availability never are used:
> >
> > void recordRequestType(CacheRequestType requestType, Addr addr);
> > bool checkResourceAvailable(CacheResourceType res, Addr addr);
> >
> > This methods are defined in cacheMemory.(hh|cc) but they are never used, I think they should be used for a more realistic simulation of the cache. What am I missing?
> >
> > Best Regards,
> > Rodrigo
> >
> >
> >
> > From: ***@hotmail.com
> > To: gem5-***@gem5.org
> > Date: Wed, 7 Oct 2015 15:27:37 +0000
> >
> > Subject: Re: [gem5-users] Different Cache R/W Latency
> >
> > Hi Andreas,
> >
> > Thanks for your answer, as you said with the classic memory system it is pretty easy to make some changes. The problem is that I am working with coherence protocols and I need to use Ruby.
> >
> > The NonCoherentCache seems a good solution, mainly if it could be used with both systems and if it returns the right access depending on the action done on the cell. It seems there is not a easy or quick way to change the R/W latency. I was thinking that changing the BankedArray could be the best way for change the latencies.
> >
> > Rodrigo
> >
> >
> > From: ***@arm.com
> > To: gem5-***@gem5.org
> > Date: Wed, 7 Oct 2015 14:41:07 +0000
> > Subject: Re: [gem5-users] Different Cache R/W Latency
> >
> > Hi Rodrigo,
> >
> > Merely an observation
with the classic memory system you can easily add an L3 and L4 cache, and as you say, changing the latencies is fairly straight forward. That said, at the moment the cache needs to have the same line size as the rest of the system. I think the best solution here is to make a NonCoherentCache that transparently sits in front of the memory controller(s), and can have any line size. This NonCoherentCache can be used both in classic and Ruby, since it does not interact with the coherency protocol.
> >
> > What we need is for someone to take a stab at creating this class, Id say starting with the class Cache, and then removing all the bits related to coherency.
> >
> > Makes sense?
> >
> > Andreas
> >
> > From: gem5-users < gem5-users-***@gem5.org > on behalf of Rodrigo Reynolds Ramírez < ***@hotmail.com >
> > Reply-To: gem5 users mailing list < gem5-***@gem5.org >
> > Date: Wednesday, 7 October 2015 07:33
> > To: gem5-users < gem5-***@gem5.org >
> > Subject: [gem5-users] Different Cache R/W Latency
> >
> > Hello Everyone,
> >
> > I am trying to simulate a LLC with other technology (STT-RAM), the problem is that I need different R/W latencies. I have found a couple of patches for the classic model, but I need to use Ruby.
> >
> > I know the access latency is divided among different parts, I need to change cell access latency. I am thinking I need to change the BankedArray.hh(cc) files, and send the access type information Read or Write. I not sure if this is the right way to get what I need. Does somebody change the access latency for the LLC in Ruby?
> >
> > Thanks
> > Rodrigo
> >
> >
> >
> > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
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