Discussion:
Different cache coherence protocols gave same stat in gem5.
(too old to reply)
Midhun P
2017-07-06 01:26:20 UTC
Permalink
I was doing comparison of different cache coherence protocols in gem5. I
took MESI 2 level, MOESI CMP directory and MOESI CMP token for that.
Benchmark i used was Moby for ARM Architecture. But in stats i got same
results for different cache coherence protocols. Please help.
Jason Lowe-Power
2017-07-06 14:21:36 UTC
Permalink
Hello,

What CPU model are you using? Ruby will only work with timing-based CPU
models (e.g., TimingSimpleCPU and O3CPU). Also, if you're using fs/se.py be
sure to specify --ruby on the command line.

There are two ways you can be sure the system you're executing is using
Ruby. 1) check the config.ini file and make sure there are Ruby caches
created (e.g., CacheMemory, Sequencer, L1Cache_controller). 2) Check the
stats.txt to be sure that the ruby objects are being accessed. The stats
should not all be 0.

Jason
Post by Midhun P
I was doing comparison of different cache coherence protocols in gem5. I
took MESI 2 level, MOESI CMP directory and MOESI CMP token for that.
Benchmark i used was Moby for ARM Architecture. But in stats i got same
results for different cache coherence protocols. Please help.
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Midhun P
2017-07-06 15:09:14 UTC
Permalink
Hi Jason,

I used the following commands for MESI Two level and MOESI CMP Directory

*MESI Two level :*

scons build/ARM/gem5.opt RUBY=True PROTOCOL=MESI_Two_level
build/ARM/gem5.opt -d m5out/1_1 configs/example/fs.py
--kernel=vmlinux.smp.ics.arm.asimbench.2.6.35
--disk-image=ARMv7a-ICS-Android.SMP.Asimbench-v3.img --frame-capture -n 4
--caches --l2cache --l1d_size=64kB --l1d_assoc=4 --l1i_size=64kB
--l1i_assoc=4 --l2_assoc=16 --l2_size=1MB --mem-size=256MB
--cpu-type=DerivO3CPU --cpu-clock=2.8GHz --machine-type=RealView_PBX
--os-type=android-ics --mem-type=LPDDR3_1600_x32 --script
~/asimbench/asimbench_boot_scripts/bbench.rcS


*MOESI CMP Dir :*
scons build/ARM/gem5.opt RUBY=True PROTOCOL=MOESI_CMP_token
build/ARM/gem5.opt -d m5out/1_1 configs/example/fs.py
--kernel=vmlinux.smp.ics.arm.asimbench.2.6.35
--disk-image=ARMv7a-ICS-Android.SMP.Asimbench-v3.img --frame-capture -n 4
--caches --l2cache --l1d_size=64kB --l1d_assoc=4 --l1i_size=64kB
--l1i_assoc=4 --l2_assoc=16 --l2_size=1MB --mem-size=256MB
--cpu-type=DerivO3CPU --cpu-clock=2.8GHz --machine-type=RealView_PBX
--os-type=android-ics --mem-type=LPDDR3_1600_x32 --script
~/asimbench/asimbench_boot_scripts/bbench.rcS

Please help.

Regards,

Midhun P
Post by Jason Lowe-Power
Hello,
What CPU model are you using? Ruby will only work with timing-based CPU
models (e.g., TimingSimpleCPU and O3CPU). Also, if you're using fs/se.py be
sure to specify --ruby on the command line.
There are two ways you can be sure the system you're executing is using
Ruby. 1) check the config.ini file and make sure there are Ruby caches
created (e.g., CacheMemory, Sequencer, L1Cache_controller). 2) Check the
stats.txt to be sure that the ruby objects are being accessed. The stats
should not all be 0.
Jason
Post by Midhun P
I was doing comparison of different cache coherence protocols in gem5. I
took MESI 2 level, MOESI CMP directory and MOESI CMP token for that.
Benchmark i used was Moby for ARM Architecture. But in stats i got same
results for different cache coherence protocols. Please help.
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
--
Regards,

Midhun P
mail to : ***@gmail.com
***@live.com
Mobile : +91-9946001223 <***@ymail.com>
Jason Lowe-Power
2017-07-07 13:02:25 UTC
Permalink
Hi Midhun,

I encourage you to do 2 things. 1) look at the config.ini file to see the
*actual* system you're simulating. 2) Read through *all* of the scripts in
configs/ that fs.py touches to understand what the command line options
mean. For instance, look at all of the options you're using on your command
line in Options.py. Then trace these options through the Python config
files.

To answer your question: --caches --l2cache enables the *classic* cache
model, not Ruby. You need to use --ruby to enable Ruby.

Jason
Post by Midhun P
Hi Jason,
I used the following commands for MESI Two level and MOESI CMP Directory
*MESI Two level :*
scons build/ARM/gem5.opt RUBY=True PROTOCOL=MESI_Two_level
build/ARM/gem5.opt -d m5out/1_1 configs/example/fs.py
--kernel=vmlinux.smp.ics.arm.asimbench.2.6.35
--disk-image=ARMv7a-ICS-Android.SMP.Asimbench-v3.img --frame-capture -n 4
--caches --l2cache --l1d_size=64kB --l1d_assoc=4 --l1i_size=64kB
--l1i_assoc=4 --l2_assoc=16 --l2_size=1MB --mem-size=256MB
--cpu-type=DerivO3CPU --cpu-clock=2.8GHz --machine-type=RealView_PBX
--os-type=android-ics --mem-type=LPDDR3_1600_x32 --script
~/asimbench/asimbench_boot_scripts/bbench.rcS
*MOESI CMP Dir :*
scons build/ARM/gem5.opt RUBY=True PROTOCOL=MOESI_CMP_token
build/ARM/gem5.opt -d m5out/1_1 configs/example/fs.py
--kernel=vmlinux.smp.ics.arm.asimbench.2.6.35
--disk-image=ARMv7a-ICS-Android.SMP.Asimbench-v3.img --frame-capture -n 4
--caches --l2cache --l1d_size=64kB --l1d_assoc=4 --l1i_size=64kB
--l1i_assoc=4 --l2_assoc=16 --l2_size=1MB --mem-size=256MB
--cpu-type=DerivO3CPU --cpu-clock=2.8GHz --machine-type=RealView_PBX
--os-type=android-ics --mem-type=LPDDR3_1600_x32 --script
~/asimbench/asimbench_boot_scripts/bbench.rcS
Please help.
Regards,
Midhun P
Post by Jason Lowe-Power
Hello,
What CPU model are you using? Ruby will only work with timing-based CPU
models (e.g., TimingSimpleCPU and O3CPU). Also, if you're using fs/se.py be
sure to specify --ruby on the command line.
There are two ways you can be sure the system you're executing is using
Ruby. 1) check the config.ini file and make sure there are Ruby caches
created (e.g., CacheMemory, Sequencer, L1Cache_controller). 2) Check the
stats.txt to be sure that the ruby objects are being accessed. The stats
should not all be 0.
Jason
Post by Midhun P
I was doing comparison of different cache coherence protocols in gem5. I
took MESI 2 level, MOESI CMP directory and MOESI CMP token for that.
Benchmark i used was Moby for ARM Architecture. But in stats i got same
results for different cache coherence protocols. Please help.
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
--
Regards,
Midhun P
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Midhun P
2017-07-10 15:58:20 UTC
Permalink
Dear Jason,

I removed --cache --l2cache arguments and replaced it with --ruby. Then ran
simulation for MOESI_CMP_Directory and MOESI_CMP_Token. But then also i got
the same configuration (compared config.ini). Please help.

./build/ARM/gem5.opt -d m5out/bbench1mb configs/example/fs.py
--kernel=vmlinux.smp.ics.arm.asimbench.2.6.35
--disk-image=ARMv7a-ICS-Android.SMP.Asimbench-v3.img --frame-capture -n 4
*--ruby* --l1d_size=64kB --l1d_assoc=4 --l1i_size=64kB --l1i_assoc=4
--l2_assoc=16 --l2_size=1MB --mem-size=256MB --cpu-type=DerivO3CPU
--cpu-clock=2.8GHz --machine-type=RealView_PBX --mem-type=LPDDR3_1600_x32
--script ~/asimbench/asimbench_boot_scripts/bbench.rcS

This is the command i used to start FS simulation.

Regards,

Midhun P
Post by Jason Lowe-Power
Hi Midhun,
I encourage you to do 2 things. 1) look at the config.ini file to see the
*actual* system you're simulating. 2) Read through *all* of the scripts in
configs/ that fs.py touches to understand what the command line options
mean. For instance, look at all of the options you're using on your command
line in Options.py. Then trace these options through the Python config
files.
To answer your question: --caches --l2cache enables the *classic* cache
model, not Ruby. You need to use --ruby to enable Ruby.
Jason
Post by Midhun P
Hi Jason,
I used the following commands for MESI Two level and MOESI CMP Directory
*MESI Two level :*
scons build/ARM/gem5.opt RUBY=True PROTOCOL=MESI_Two_level
build/ARM/gem5.opt -d m5out/1_1 configs/example/fs.py
--kernel=vmlinux.smp.ics.arm.asimbench.2.6.35 --disk-image=ARMv7a-ICS-Android.SMP.Asimbench-v3.img
--frame-capture -n 4 --caches --l2cache --l1d_size=64kB --l1d_assoc=4
--l1i_size=64kB --l1i_assoc=4 --l2_assoc=16 --l2_size=1MB --mem-size=256MB
--cpu-type=DerivO3CPU --cpu-clock=2.8GHz --machine-type=RealView_PBX
--os-type=android-ics --mem-type=LPDDR3_1600_x32 --script
~/asimbench/asimbench_boot_scripts/bbench.rcS
*MOESI CMP Dir :*
scons build/ARM/gem5.opt RUBY=True PROTOCOL=MOESI_CMP_token
build/ARM/gem5.opt -d m5out/1_1 configs/example/fs.py
--kernel=vmlinux.smp.ics.arm.asimbench.2.6.35 --disk-image=ARMv7a-ICS-Android.SMP.Asimbench-v3.img
--frame-capture -n 4 --caches --l2cache --l1d_size=64kB --l1d_assoc=4
--l1i_size=64kB --l1i_assoc=4 --l2_assoc=16 --l2_size=1MB --mem-size=256MB
--cpu-type=DerivO3CPU --cpu-clock=2.8GHz --machine-type=RealView_PBX
--os-type=android-ics --mem-type=LPDDR3_1600_x32 --script
~/asimbench/asimbench_boot_scripts/bbench.rcS
Please help.
Regards,
Midhun P
Post by Jason Lowe-Power
Hello,
What CPU model are you using? Ruby will only work with timing-based CPU
models (e.g., TimingSimpleCPU and O3CPU). Also, if you're using fs/se.py be
sure to specify --ruby on the command line.
There are two ways you can be sure the system you're executing is using
Ruby. 1) check the config.ini file and make sure there are Ruby caches
created (e.g., CacheMemory, Sequencer, L1Cache_controller). 2) Check the
stats.txt to be sure that the ruby objects are being accessed. The stats
should not all be 0.
Jason
Post by Midhun P
I was doing comparison of different cache coherence protocols in gem5.
I took MESI 2 level, MOESI CMP directory and MOESI CMP token for that.
Benchmark i used was Moby for ARM Architecture. But in stats i got same
results for different cache coherence protocols. Please help.
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
--
Regards,
Midhun P
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
--
Regards,

Midhun P
mail to : ***@gmail.com
***@live.com
Mobile : +91-9946001223 <***@ymail.com>
Jason Lowe-Power
2017-07-11 14:27:57 UTC
Permalink
Hi Midhun,

That command line looks reasonable to me. I'm not sure what is causing your
unexpected behavior. Again, I encourage you to read through *all* of the
scripts in configs/ that fs.py touches to understand what the command line
options mean. Maybe some option you're setting is overriding the --ruby
option (very likely).

Jason
Post by Midhun P
Dear Jason,
I removed --cache --l2cache arguments and replaced it with --ruby. Then
ran simulation for MOESI_CMP_Directory and MOESI_CMP_Token. But then also i
got the same configuration (compared config.ini). Please help.
./build/ARM/gem5.opt -d m5out/bbench1mb configs/example/fs.py
--kernel=vmlinux.smp.ics.arm.asimbench.2.6.35
--disk-image=ARMv7a-ICS-Android.SMP.Asimbench-v3.img --frame-capture -n 4
*--ruby* --l1d_size=64kB --l1d_assoc=4 --l1i_size=64kB --l1i_assoc=4
--l2_assoc=16 --l2_size=1MB --mem-size=256MB --cpu-type=DerivO3CPU
--cpu-clock=2.8GHz --machine-type=RealView_PBX --mem-type=LPDDR3_1600_x32
--script ~/asimbench/asimbench_boot_scripts/bbench.rcS
This is the command i used to start FS simulation.
Regards,
Midhun P
Post by Jason Lowe-Power
Hi Midhun,
I encourage you to do 2 things. 1) look at the config.ini file to see the
*actual* system you're simulating. 2) Read through *all* of the scripts in
configs/ that fs.py touches to understand what the command line options
mean. For instance, look at all of the options you're using on your command
line in Options.py. Then trace these options through the Python config
files.
To answer your question: --caches --l2cache enables the *classic* cache
model, not Ruby. You need to use --ruby to enable Ruby.
Jason
Post by Midhun P
Hi Jason,
I used the following commands for MESI Two level and MOESI CMP Directory
*MESI Two level :*
scons build/ARM/gem5.opt RUBY=True PROTOCOL=MESI_Two_level
build/ARM/gem5.opt -d m5out/1_1 configs/example/fs.py
--kernel=vmlinux.smp.ics.arm.asimbench.2.6.35
--disk-image=ARMv7a-ICS-Android.SMP.Asimbench-v3.img --frame-capture -n 4
--caches --l2cache --l1d_size=64kB --l1d_assoc=4 --l1i_size=64kB
--l1i_assoc=4 --l2_assoc=16 --l2_size=1MB --mem-size=256MB
--cpu-type=DerivO3CPU --cpu-clock=2.8GHz --machine-type=RealView_PBX
--os-type=android-ics --mem-type=LPDDR3_1600_x32 --script
~/asimbench/asimbench_boot_scripts/bbench.rcS
*MOESI CMP Dir :*
scons build/ARM/gem5.opt RUBY=True PROTOCOL=MOESI_CMP_token
build/ARM/gem5.opt -d m5out/1_1 configs/example/fs.py
--kernel=vmlinux.smp.ics.arm.asimbench.2.6.35
--disk-image=ARMv7a-ICS-Android.SMP.Asimbench-v3.img --frame-capture -n 4
--caches --l2cache --l1d_size=64kB --l1d_assoc=4 --l1i_size=64kB
--l1i_assoc=4 --l2_assoc=16 --l2_size=1MB --mem-size=256MB
--cpu-type=DerivO3CPU --cpu-clock=2.8GHz --machine-type=RealView_PBX
--os-type=android-ics --mem-type=LPDDR3_1600_x32 --script
~/asimbench/asimbench_boot_scripts/bbench.rcS
Please help.
Regards,
Midhun P
Post by Jason Lowe-Power
Hello,
What CPU model are you using? Ruby will only work with timing-based CPU
models (e.g., TimingSimpleCPU and O3CPU). Also, if you're using fs/se.py be
sure to specify --ruby on the command line.
There are two ways you can be sure the system you're executing is using
Ruby. 1) check the config.ini file and make sure there are Ruby caches
created (e.g., CacheMemory, Sequencer, L1Cache_controller). 2) Check the
stats.txt to be sure that the ruby objects are being accessed. The stats
should not all be 0.
Jason
Post by Midhun P
I was doing comparison of different cache coherence protocols in gem5.
I took MESI 2 level, MOESI CMP directory and MOESI CMP token for that.
Benchmark i used was Moby for ARM Architecture. But in stats i got same
results for different cache coherence protocols. Please help.
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
--
Regards,
Midhun P
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
--
Regards,
Midhun P
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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