Discussion:
gem5-users@gem5.org
(too old to reply)
Uzair Sharif
2015-11-25 10:36:09 UTC
Permalink
Hi,Is it possible that I can hook CPU model within full system to SystemC?? I have gone through util/tlm example but that hooks the mem_bus to SystemC module. Can I just simply disable all caches, membus, mem_ctrls and connect CPU's icache_port, dcache_port to ExternalSlave (like in the TLM example) and implement the entire memory system functionality in SystemC?? What should I be careful about in doing this??Regards
Uzair Sharif
2015-11-25 10:43:20 UTC
Permalink
Hi,
Is it possible that I can hook CPU model within full system to SystemC?? I have gone through util/tlm example but that hooks the mem_bus to SystemC module. Can I just simply disable all caches, membus, mem_ctrls and connect CPU's icache_port, dcache_port to ExternalSlave (like in the TLM example) and implement the entire memory system functionality in SystemC?? What should I be careful about in doing this??
Regards,uzair
Abdul Mutaal
2015-11-25 13:34:14 UTC
Permalink
Hi,

I believe it would be tough to realize a system in gem5 without system bus.
It would suggest you to keep the membus and play with its parameters so
that it doesn't effect your simulation (latency or bandwidth).

I haven't tried but you can also look to run in SE mode. FS seems to be too
complex for your architecture.

Regards,

Abdul Mutaal

2015-11-25 11:43 GMT+01:00 Uzair Sharif <***@live.com>:

> Hi,
>
>
> Is it possible that I can hook CPU model within full system to SystemC?? I
> have gone through util/tlm example but that hooks the mem_bus to SystemC
> module.
>
> Can I just simply disable all caches, membus, mem_ctrls and connect CPU's
> icache_port, dcache_port to ExternalSlave (like in the TLM example) and
> implement the entire memory system functionality in SystemC?? What should I
> be careful about in doing this??
>
>
> Regards,
>
> uzair
>
> _______________________________________________
> gem5-users mailing list
> gem5-***@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>



--

Regards,
Abdul Mutaal
Andreas Hansson
2015-11-25 13:37:26 UTC
Permalink
Hi Uzair,

I think conceptually you should be find doing what you suggest: Connect each CPU core directly to two ExternalSlave ports

As Abdul points out though
this is really jumping in at the deep end.

Andreas

From: gem5-users <gem5-users-***@gem5.org<mailto:gem5-users-***@gem5.org>> on behalf of Abdul Mutaal <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Wednesday, 25 November 2015 at 13:34
To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] SystemC coupling with gem5

Hi,

I believe it would be tough to realize a system in gem5 without system bus. It would suggest you to keep the membus and play with its parameters so that it doesn't effect your simulation (latency or bandwidth).

I haven't tried but you can also look to run in SE mode. FS seems to be too complex for your architecture.

Regards,

Abdul Mutaal

2015-11-25 11:43 GMT+01:00 Uzair Sharif <***@live.com<mailto:***@live.com>>:

Hi,


Is it possible that I can hook CPU model within full system to SystemC?? I have gone through util/tlm example but that hooks the mem_bus to SystemC module.

Can I just simply disable all caches, membus, mem_ctrls and connect CPU's icache_port, dcache_port to ExternalSlave (like in the TLM example) and implement the entire memory system functionality in SystemC?? What should I be careful about in doing this??


Regards,

uzair

_______________________________________________
gem5-users mailing list
gem5-***@gem5.org<mailto:gem5-***@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users



--

Regards,
Abdul Mutaal


IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Uzair Sharif
2015-11-25 14:19:42 UTC
Permalink
Hi,
Thanks guys for the feedback. Well sofar I modified /configs/learning_gem5/part1/simple.py system to hook up single CPU's cache ports (i/d) as well as system_port to 3 ExternalSlave ports with membus disabled. From the logs I can see that binary for hello_world is loaded followed by a block of memory written via dcache_port. After that the simulation starts running with IFetches and it seems to work fine but I end up with an assertion failure:
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
0 s (=) : sc_main Port Found
0 s (=) : /IEEE_Std_1666/deprecated deprecated constructor: sc_time(uint64,bool)
gem5.opt.sc: build/ARM/mem/request.hh:569: uint64_t Request::getExtraData() const: Assertion `privateFlags.isSet(VALID_EXTRA_DATA)' failed.
Program aborted at tick 80160000
Aborted (core dumped)
Can you guys point out why this assertion fails as I am not familiar with gem5 internals?? Is it related to the use of external memory system?? Have I messed up somewhere??

Regarding the use of SystemC memory system, actually I have already developed SystemC models and used them in ARMv7 based architectures but now I want to integrate them with ARMv8 based mutlicore systems which I think are supported well by gem5. I can use the system.membus-hook-to-SystemC approach but I need to somehow figure out which smp-core actually initiated the memory transaction for my cache-algos to work. Is this possible within gem5 that somehow I can know initiator-smp core via some sort of tlm_extension or something else within the SystemC port/target?? This would be quite useful and allow me to just hook the membus which is already done by Matthias work
Regards, uzair

From: ***@arm.com
To: gem5-***@gem5.org
Date: Wed, 25 Nov 2015 13:37:26 +0000
Subject: Re: [gem5-users] SystemC coupling with gem5






Hi Uzair,



I think conceptually you should be find doing what you suggest: Connect each CPU core directly to two ExternalSlave ports



As Abdul points out though…this is really jumping in at the deep end.



Andreas





From: gem5-users <gem5-users-***@gem5.org> on behalf of Abdul Mutaal <***@gmail.com>

Reply-To: gem5 users mailing list <gem5-***@gem5.org>

Date: Wednesday, 25 November 2015 at 13:34

To: gem5 users mailing list <gem5-***@gem5.org>

Subject: Re: [gem5-users] SystemC coupling with gem5







Hi,



I believe it would be tough to realize a system in gem5 without system bus. It would suggest you to keep the membus and play with its parameters so that it doesn't effect your simulation (latency or bandwidth).



I haven't tried but you can also look to run in SE mode. FS seems to be too complex for your architecture.



Regards,



Abdul Mutaal



2015-11-25 11:43 GMT+01:00 Uzair Sharif
<***@live.com>:







Hi,





Is it possible that I can hook CPU model within full system to SystemC?? I have gone through util/tlm example but that hooks the mem_bus to SystemC module.

Can I just simply disable all caches, membus, mem_ctrls and connect CPU's icache_port, dcache_port to ExternalSlave (like in the TLM example) and implement the entire memory system functionality in SystemC?? What should I be careful about in doing this??





Regards,

uzair






_______________________________________________

gem5-users mailing list

gem5-***@gem5.org

http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users









--






Regards,
Abdul Mutaal











IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for
any purpose, or store or copy the information in any medium. Thank you.
Uzair Sharif
2015-11-25 14:47:00 UTC
Permalink
Hi,
I forgot to mention that in this simple.py setup even with membus hooked to external world (like in util/tlm/tlm.py) I get the same assertion error so this issue is atleast not related to directly hooking CPU to SystemC.
Regards, uzair
From: ***@live.com
To: gem5-***@gem5.org
Date: Wed, 25 Nov 2015 15:19:42 +0100
Subject: Re: [gem5-users] SystemC coupling with gem5




Hi,
Thanks guys for the feedback. Well sofar I modified /configs/learning_gem5/part1/simple.py system to hook up single CPU's cache ports (i/d) as well as system_port to 3 ExternalSlave ports with membus disabled. From the logs I can see that binary for hello_world is loaded followed by a block of memory written via dcache_port. After that the simulation starts running with IFetches and it seems to work fine but I end up with an assertion failure:
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
0 s (=) : sc_main Port Found
0 s (=) : /IEEE_Std_1666/deprecated deprecated constructor: sc_time(uint64,bool)
gem5.opt.sc: build/ARM/mem/request.hh:569: uint64_t Request::getExtraData() const: Assertion `privateFlags.isSet(VALID_EXTRA_DATA)' failed.
Program aborted at tick 80160000
Aborted (core dumped)
Can you guys point out why this assertion fails as I am not familiar with gem5 internals?? Is it related to the use of external memory system?? Have I messed up somewhere??

Regarding the use of SystemC memory system, actually I have already developed SystemC models and used them in ARMv7 based architectures but now I want to integrate them with ARMv8 based mutlicore systems which I think are supported well by gem5. I can use the system.membus-hook-to-SystemC approach but I need to somehow figure out which smp-core actually initiated the memory transaction for my cache-algos to work. Is this possible within gem5 that somehow I can know initiator-smp core via some sort of tlm_extension or something else within the SystemC port/target?? This would be quite useful and allow me to just hook the membus which is already done by Matthias work
Regards, uzair

From: ***@arm.com
To: gem5-***@gem5.org
Date: Wed, 25 Nov 2015 13:37:26 +0000
Subject: Re: [gem5-users] SystemC coupling with gem5






Hi Uzair,



I think conceptually you should be find doing what you suggest: Connect each CPU core directly to two ExternalSlave ports



As Abdul points out though…this is really jumping in at the deep end.



Andreas





From: gem5-users <gem5-users-***@gem5.org> on behalf of Abdul Mutaal <***@gmail.com>

Reply-To: gem5 users mailing list <gem5-***@gem5.org>

Date: Wednesday, 25 November 2015 at 13:34

To: gem5 users mailing list <gem5-***@gem5.org>

Subject: Re: [gem5-users] SystemC coupling with gem5







Hi,



I believe it would be tough to realize a system in gem5 without system bus. It would suggest you to keep the membus and play with its parameters so that it doesn't effect your simulation (latency or bandwidth).



I haven't tried but you can also look to run in SE mode. FS seems to be too complex for your architecture.



Regards,



Abdul Mutaal



2015-11-25 11:43 GMT+01:00 Uzair Sharif
<***@live.com>:







Hi,





Is it possible that I can hook CPU model within full system to SystemC?? I have gone through util/tlm example but that hooks the mem_bus to SystemC module.

Can I just simply disable all caches, membus, mem_ctrls and connect CPU's icache_port, dcache_port to ExternalSlave (like in the TLM example) and implement the entire memory system functionality in SystemC?? What should I be careful about in doing this??





Regards,

uzair






_______________________________________________

gem5-users mailing list

gem5-***@gem5.org

http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users









--






Regards,
Abdul Mutaal











IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for
any purpose, or store or copy the information in any medium. Thank you.
Andreas Hansson
2015-11-25 14:51:06 UTC
Permalink
Hi Uzair,

Your memory system needs to implement the same semantics as the gem5 memory system (not just read and write). Have a look at SimpleMemory in src/mem for what you need to do. Depending on how you bridge to SystemC, you need to also translate from TLM to gem5 packets, also for these more complex memory commands.

Andreas

From: gem5-users <gem5-users-***@gem5.org<mailto:gem5-users-***@gem5.org>> on behalf of Uzair Sharif <***@live.com<mailto:***@live.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Wednesday, 25 November 2015 at 14:47
To: gem5 <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] SystemC coupling with gem5

Hi,

I forgot to mention that in this simple.py setup even with membus hooked to external world (like in util/tlm/tlm.py) I get the same assertion error so this issue is atleast not related to directly hooking CPU to SystemC.

Regards, uzair

________________________________
From: ***@live.com<mailto:***@live.com>
To: gem5-***@gem5.org<mailto:gem5-***@gem5.org>
Date: Wed, 25 Nov 2015 15:19:42 +0100
Subject: Re: [gem5-users] SystemC coupling with gem5

Hi,

Thanks guys for the feedback. Well sofar I modified /configs/learning_gem5/part1/simple.py system to hook up single CPU's cache ports (i/d) as well as system_port to 3 ExternalSlave ports with membus disabled. From the logs I can see that binary for hello_world is loaded followed by a block of memory written via dcache_port. After that the simulation starts running with IFetches and it seems to work fine but I end up with an assertion failure:

0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000

0 s (=) : sc_main Port Found

0 s (=) : /IEEE_Std_1666/deprecated deprecated constructor: sc_time(uint64,bool)

gem5.opt.sc: build/ARM/mem/request.hh:569: uint64_t Request::getExtraData() const: Assertion `privateFlags.isSet(VALID_EXTRA_DATA)'
failed.

Program aborted at tick 80160000

Aborted (core dumped)

Can you guys point out why this assertion fails as I am not familiar with gem5 internals?? Is it related to the use of external memory system?? Have I messed up somewhere??


Regarding the use of SystemC memory system, actually I have already developed SystemC models and used them in ARMv7 based architectures but now I want to integrate them with ARMv8 based mutlicore systems which I think are supported well by gem5. I can use the system.membus-hook-to-SystemC approach but I need to somehow figure out which smp-core actually initiated the memory transaction for my cache-algos to work. Is this possible within gem5 that somehow I can know initiator-smp core via some sort of tlm_extension or something else within the SystemC port/target?? This would be quite useful and allow me to just hook the membus which is already done by Matthias work

Regards, uzair


________________________________
From: ***@arm.com<mailto:***@arm.com>
To: gem5-***@gem5.org<mailto:gem5-***@gem5.org>
Date: Wed, 25 Nov 2015 13:37:26 +0000
Subject: Re: [gem5-users] SystemC coupling with gem5

Hi Uzair,

I think conceptually you should be find doing what you suggest: Connect each CPU core directly to two ExternalSlave ports

As Abdul points out though
this is really jumping in at the deep end.

Andreas

From: gem5-users <gem5-users-***@gem5.org<mailto:gem5-users-***@gem5.org>> on behalf of Abdul Mutaal <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Wednesday, 25 November 2015 at 13:34
To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] SystemC coupling with gem5

Hi,

I believe it would be tough to realize a system in gem5 without system bus. It would suggest you to keep the membus and play with its parameters so that it doesn't effect your simulation (latency or bandwidth).

I haven't tried but you can also look to run in SE mode. FS seems to be too complex for your architecture.

Regards,

Abdul Mutaal

2015-11-25 11:43 GMT+01:00 Uzair Sharif <***@live.com<mailto:***@live.com>>:

Hi,


Is it possible that I can hook CPU model within full system to SystemC?? I have gone through util/tlm example but that hooks the mem_bus to SystemC module.

Can I just simply disable all caches, membus, mem_ctrls and connect CPU's icache_port, dcache_port to ExternalSlave (like in the TLM example) and implement the entire memory system functionality in SystemC?? What should I be careful about in doing this??


Regards,

uzair

_______________________________________________
gem5-users mailing list
gem5-***@gem5.org<mailto:gem5-***@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users



--

Regards,
Abdul Mutaal


IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
_______________________________________________ gem5-users mailing list gem5-***@gem5.org<mailto:gem5-***@gem5.org> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

_______________________________________________ gem5-users mailing list gem5-***@gem5.org<mailto:gem5-***@gem5.org> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Uzair Sharif
2015-11-25 15:16:59 UTC
Permalink
Hi,
Thanks for the feedback. Ok this makes sense. I will now look further into gem5 internals then. By the way, right now I am using /utils/tlm/ patch for hooking to SystemC world and was hoping that these semantics would have already been dealt with in the patch as the fs.py works with external SystemC so I assumed it should work with simple.py system if used unmodified but I am unable to get that system running due to the mentioned assertion failure.
Regars, uzair

From: ***@arm.com
To: gem5-***@gem5.org
Date: Wed, 25 Nov 2015 14:51:06 +0000
Subject: Re: [gem5-users] SystemC coupling with gem5






Hi Uzair,



Your memory system needs to implement the same semantics as the gem5 memory system (not just read and write). Have a look at SimpleMemory in src/mem for what you need to do. Depending on how you bridge to SystemC, you need to also translate from TLM to
gem5 packets, also for these more complex memory commands.



Andreas





From: gem5-users <gem5-users-***@gem5.org> on behalf of Uzair Sharif <***@live.com>

Reply-To: gem5 users mailing list <gem5-***@gem5.org>

Date: Wednesday, 25 November 2015 at 14:47

To: gem5 <gem5-***@gem5.org>

Subject: Re: [gem5-users] SystemC coupling with gem5







Hi,



I forgot to mention that in this simple.py setup even with membus hooked to external world (like in util/tlm/tlm.py) I get the same assertion error so this issue is atleast not related to directly hooking CPU to SystemC.



Regards, uzair




From: ***@live.com

To: gem5-***@gem5.org

Date: Wed, 25 Nov 2015 15:19:42 +0100

Subject: Re: [gem5-users] SystemC coupling with gem5




Hi,



Thanks guys for the feedback. Well sofar I modified /configs/learning_gem5/part1/simple.py system to hook up single CPU's cache ports (i/d) as well as system_port to 3 ExternalSlave ports with
membus disabled. From the logs I can see that binary for hello_world is loaded followed by a block of memory written via
dcache_port. After that the simulation starts running with IFetches and it seems to work fine but I end up with an assertion failure:




0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000



0 s (=) : sc_main Port Found



0 s (=) : /IEEE_Std_1666/deprecated deprecated constructor: sc_time(uint64,bool)



gem5.opt.sc: build/ARM/mem/request.hh:569: uint64_t Request::getExtraData() const: Assertion `privateFlags.isSet(VALID_EXTRA_DATA)'
failed.



Program aborted at tick 80160000



Aborted (core dumped)



Can you guys point out why this assertion fails as I am not familiar with gem5 internals?? Is it related to the use of external memory system?? Have I messed up somewhere??






Regarding the use of SystemC memory system, actually I have already developed SystemC models and used them in ARMv7 based architectures but now I want to integrate them with ARMv8 based mutlicore systems which I think are supported well by gem5. I can
use the system.membus-hook-to-SystemC approach but I need to somehow figure out which smp-core actually initiated the memory transaction for my cache-algos to work. Is this possible within gem5 that somehow I can know initiator-smp core via some sort
of tlm_extension or something else within the SystemC port/target?? This would be quite useful and allow me to just hook the
membus which is already done by Matthias work



Regards, uzair







From: ***@arm.com

To: gem5-***@gem5.org

Date: Wed, 25 Nov 2015 13:37:26 +0000

Subject: Re: [gem5-users] SystemC coupling with gem5



Hi Uzair,



I think conceptually you should be find doing what you suggest: Connect each CPU core directly to two ExternalSlave ports



As Abdul points out though…this is really jumping in at the deep end.



Andreas





From: gem5-users <gem5-users-***@gem5.org> on behalf of Abdul Mutaal <***@gmail.com>

Reply-To: gem5 users mailing list <gem5-***@gem5.org>

Date: Wednesday, 25 November 2015 at 13:34

To: gem5 users mailing list <gem5-***@gem5.org>

Subject: Re: [gem5-users] SystemC coupling with gem5







Hi,



I believe it would be tough to realize a system in gem5 without system bus. It would suggest you to keep the membus and play with its parameters so that it doesn't effect your simulation (latency or bandwidth).



I haven't tried but you can also look to run in SE mode. FS seems to be too complex for your architecture.



Regards,



Abdul Mutaal



2015-11-25 11:43 GMT+01:00 Uzair Sharif
<***@live.com>:







Hi,





Is it possible that I can hook CPU model within full system to SystemC?? I have gone through util/tlm example but that hooks the mem_bus to SystemC module.

Can I just simply disable all caches, membus, mem_ctrls and connect CPU's icache_port, dcache_port to ExternalSlave (like in the TLM example) and implement the entire memory system functionality in SystemC?? What should I be careful about in doing this??





Regards,

uzair






_______________________________________________

gem5-users mailing list

gem5-***@gem5.org

http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users









--






Regards,
Abdul Mutaal











IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for
any purpose, or store or copy the information in any medium. Thank you.

_______________________________________________ gem5-users mailing list
gem5-***@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users




_______________________________________________ gem5-users mailing list
gem5-***@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users




IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for
any purpose, or store or copy the information in any medium. Thank you.
Andreas Hansson
2015-11-25 15:20:57 UTC
Permalink
Hi Uzair,

The example only covers very basic read and write commands. If all you do is attach an external memory/device that should be fine. If you want to replace the whole memory system you have to deal with all the supported (or at least used) commands.

It would be a nice addition to the wrappers, so please post a patch if you get this all working.

Andreas

From: gem5-users <gem5-users-***@gem5.org<mailto:gem5-users-***@gem5.org>> on behalf of Uzair Sharif <***@live.com<mailto:***@live.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Wednesday, 25 November 2015 at 15:16
To: gem5 <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] SystemC coupling with gem5

Hi,

Thanks for the feedback. Ok this makes sense. I will now look further into gem5 internals then. By the way, right now I am using /utils/tlm/ patch for hooking to SystemC world and was hoping that these semantics would have already been dealt with in the patch as the fs.py works with external SystemC so I assumed it should work with simple.py system if used unmodified but I am unable to get that system running due to the mentioned assertion failure.

Regars, uzair

________________________________
From: ***@arm.com<mailto:***@arm.com>
To: gem5-***@gem5.org<mailto:gem5-***@gem5.org>
Date: Wed, 25 Nov 2015 14:51:06 +0000
Subject: Re: [gem5-users] SystemC coupling with gem5

Hi Uzair,

Your memory system needs to implement the same semantics as the gem5 memory system (not just read and write). Have a look at SimpleMemory in src/mem for what you need to do. Depending on how you bridge to SystemC, you need to also translate from TLM to gem5 packets, also for these more complex memory commands.

Andreas

From: gem5-users <gem5-users-***@gem5.org<mailto:gem5-users-***@gem5.org>> on behalf of Uzair Sharif <***@live.com<mailto:***@live.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Wednesday, 25 November 2015 at 14:47
To: gem5 <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] SystemC coupling with gem5

Hi,

I forgot to mention that in this simple.py setup even with membus hooked to external world (like in util/tlm/tlm.py) I get the same assertion error so this issue is atleast not related to directly hooking CPU to SystemC.

Regards, uzair

________________________________
From: ***@live.com<mailto:***@live.com>
To: gem5-***@gem5.org<mailto:gem5-***@gem5.org>
Date: Wed, 25 Nov 2015 15:19:42 +0100
Subject: Re: [gem5-users] SystemC coupling with gem5

Hi,

Thanks guys for the feedback. Well sofar I modified /configs/learning_gem5/part1/simple.py system to hook up single CPU's cache ports (i/d) as well as system_port to 3 ExternalSlave ports with membus disabled. From the logs I can see that binary for hello_world is loaded followed by a block of memory written via dcache_port. After that the simulation starts running with IFetches and it seems to work fine but I end up with an assertion failure:

0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000

0 s (=) : sc_main Port Found

0 s (=) : /IEEE_Std_1666/deprecated deprecated constructor: sc_time(uint64,bool)

gem5.opt.sc: build/ARM/mem/request.hh:569: uint64_t Request::getExtraData() const: Assertion `privateFlags.isSet(VALID_EXTRA_DATA)'
failed.

Program aborted at tick 80160000

Aborted (core dumped)

Can you guys point out why this assertion fails as I am not familiar with gem5 internals?? Is it related to the use of external memory system?? Have I messed up somewhere??


Regarding the use of SystemC memory system, actually I have already developed SystemC models and used them in ARMv7 based architectures but now I want to integrate them with ARMv8 based mutlicore systems which I think are supported well by gem5. I can use the system.membus-hook-to-SystemC approach but I need to somehow figure out which smp-core actually initiated the memory transaction for my cache-algos to work. Is this possible within gem5 that somehow I can know initiator-smp core via some sort of tlm_extension or something else within the SystemC port/target?? This would be quite useful and allow me to just hook the membus which is already done by Matthias work

Regards, uzair


________________________________
From: ***@arm.com<mailto:***@arm.com>
To: gem5-***@gem5.org<mailto:gem5-***@gem5.org>
Date: Wed, 25 Nov 2015 13:37:26 +0000
Subject: Re: [gem5-users] SystemC coupling with gem5

Hi Uzair,

I think conceptually you should be find doing what you suggest: Connect each CPU core directly to two ExternalSlave ports

As Abdul points out though
this is really jumping in at the deep end.

Andreas

From: gem5-users <gem5-users-***@gem5.org<mailto:gem5-users-***@gem5.org>> on behalf of Abdul Mutaal <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Wednesday, 25 November 2015 at 13:34
To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] SystemC coupling with gem5

Hi,

I believe it would be tough to realize a system in gem5 without system bus. It would suggest you to keep the membus and play with its parameters so that it doesn't effect your simulation (latency or bandwidth).

I haven't tried but you can also look to run in SE mode. FS seems to be too complex for your architecture.

Regards,

Abdul Mutaal

2015-11-25 11:43 GMT+01:00 Uzair Sharif <***@live.com<mailto:***@live.com>>:

Hi,


Is it possible that I can hook CPU model within full system to SystemC?? I have gone through util/tlm example but that hooks the mem_bus to SystemC module.

Can I just simply disable all caches, membus, mem_ctrls and connect CPU's icache_port, dcache_port to ExternalSlave (like in the TLM example) and implement the entire memory system functionality in SystemC?? What should I be careful about in doing this??


Regards,

uzair

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Regards,
Abdul Mutaal


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