Discussion:
Running two SimpleDram instances simulataniously
(too old to reply)
Ahmad Hassan
2013-10-25 10:18:06 UTC
Permalink
Thanks Andreas for the details. As I want to add a logic of which virtual
addresses should go to which memory controller (DDR3 or PCM), so I was
thinking that I would have one memory port that receives packet from the
system and then I add up logic of virtual address and call the appropriate
memory controller (DDR3 or PCM) afterwards. Do you suggest the same?

Otherwise if we add two memory controller ports to the memory bus then what
place would I add the logic of which virtual address should go to which
controller?

CC'ing user list.

Thanks.

Best Regards, Ahmad
Hi Ahmad,
You can instantiate as many controller as you want, all you have to do
is edit the python files. You can either try and add it as an option to
fs.py or similar, or manually create a system in a separate .py file.
You can simply do system.ddr3_ctrl = SimpleDDR3() and system.pcm_ctrl =
SimplePCM() (you have to create the latter class). You pass the address
range as a parameter to each controller. When you connect them to the bus
they will automatically be updating the address map in the bus.
Good luck.
As a final note, please stick to the mailing list :-)
Andreas
Date: Wednesday, 23 October 2013 20:29
Subject: Re: Running two SimpleDram instances simulataniously
Or more simply, how would it be possible to use both "SimpleLPDDR2_S4"
and "SimpleDDR3" simultaneously. I will redirect some virtual addresses
to SimpleLPDDR2_S4 and some to SimpleDDR3.
Thanks.
kind Regards, Ahmad
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
Andreas Hansson
2013-10-25 10:30:29 UTC
Permalink
Hi Ahmad,

When you instantiate the controllers you decide what physical address they occupy (also in the case of multi-channel controllers where we use striping between them).

If you want to control the virtual to physical mapping, I am afraid you have to figure out a way to control the page allocation in the OS. Perhaps someone on the list knows a sensible way of achieving this without too much Linux brain surgery.

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Date: Friday, 25 October 2013 11:18
To: Andreas Hansson <***@arm.com<mailto:***@arm.com>>, gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: Running two SimpleDram instances simulataniously

Thanks Andreas for the details. As I want to add a logic of which virtual addresses should go to which memory controller (DDR3 or PCM), so I was thinking that I would have one memory port that receives packet from the system and then I add up logic of virtual address and call the appropriate memory controller (DDR3 or PCM) afterwards. Do you suggest the same?

Otherwise if we add two memory controller ports to the memory bus then what place would I add the logic of which virtual address should go to which controller?

CC'ing user list.

Thanks.

Best Regards, Ahmad


On 24 October 2013 19:28, Andreas Hansson <***@arm.com<mailto:***@arm.com>> wrote:
Hi Ahmad,

You can instantiate as many controller as you want, all you have to do is edit the python files. You can either try and add it as an option to fs.py or similar, or manually create a system in a separate .py file.

You can simply do system.ddr3_ctrl = SimpleDDR3() and system.pcm_ctrl = SimplePCM() (you have to create the latter class). You pass the address range as a parameter to each controller. When you connect them to the bus they will automatically be updating the address map in the bus.

Good luck.

As a final note, please stick to the mailing list :-)

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Date: Wednesday, 23 October 2013 20:29
To: Andreas Hansson <***@arm.com<mailto:***@arm.com>>
Subject: Re: Running two SimpleDram instances simulataniously

Or more simply, how would it be possible to use both "SimpleLPDDR2_S4" and "SimpleDDR3" simultaneously. I will redirect some virtual addresses to SimpleLPDDR2_S4 and some to SimpleDDR3.

Thanks.

kind Regards, Ahmad


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Ahmad Hassan
2013-10-25 10:40:28 UTC
Permalink
Post by Andreas Hansson
If you want to control the virtual to physical mapping, I am afraid you
have to figure out a way to control the page allocation in the OS. Perhaps
someone on the list knows a sensible way of achieving this without too much
Linux brain surgery.
OS is not required. In my case, I have the list of virtual address which I
know that they should always go through DDR3 timing model and the rest of
the virtual addresses should go to PCM timing model. In the integrated
patch of dramsim2 with GEM5 it was trivial where I added this logic in
"DRAMSim2::MemoryPort::recvTimingReq". I instantiated two instances of
dramsim2 (one with DDR3 timing and second with PCM timing). Then
in recvTimingReq method I was checking the incoming virtual address and
then calling appropriate dramsim2 instance accordingly.

I want to do similar thing with SimpleDRAM model of Gem5. Is it possible?

Thanks.

kind Regards, Ahmad
Post by Andreas Hansson
Andreas
Date: Friday, 25 October 2013 11:18
Subject: Re: Running two SimpleDram instances simulataniously
Thanks Andreas for the details. As I want to add a logic of which
virtual addresses should go to which memory controller (DDR3 or PCM), so I
was thinking that I would have one memory port that receives packet from
the system and then I add up logic of virtual address and call the
appropriate memory controller (DDR3 or PCM) afterwards. Do you suggest the
same?
Otherwise if we add two memory controller ports to the memory bus then
what place would I add the logic of which virtual address should go to
which controller?
CC'ing user list.
Thanks.
Best Regards, Ahmad
Hi Ahmad,
You can instantiate as many controller as you want, all you have to do
is edit the python files. You can either try and add it as an option to
fs.py or similar, or manually create a system in a separate .py file.
You can simply do system.ddr3_ctrl = SimpleDDR3() and system.pcm_ctrl =
SimplePCM() (you have to create the latter class). You pass the address
range as a parameter to each controller. When you connect them to the bus
they will automatically be updating the address map in the bus.
Good luck.
As a final note, please stick to the mailing list :-)
Andreas
Date: Wednesday, 23 October 2013 20:29
Subject: Re: Running two SimpleDram instances simulataniously
Or more simply, how would it be possible to use both "SimpleLPDDR2_S4"
and "SimpleDDR3" simultaneously. I will redirect some virtual addresses
to SimpleLPDDR2_S4 and some to SimpleDDR3.
Thanks.
kind Regards, Ahmad
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
Andreas Hansson
2013-10-25 10:46:37 UTC
Permalink
Hi Ahmad,

Doing address decoding based on virtual addresses in the interconnect (which is what you suggest), is something I would greatly advise against. If you really want to do this, the place you need to hack (i.m.h.o) is the Bus base class. The function findPort determines where to route the packet based on the physical address.

Once again, I would advise against using anything but the physical address for the address decoding, and rather make sure your physical page mapping does what you want.

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Date: Friday, 25 October 2013 11:40
To: Andreas Hansson <***@arm.com<mailto:***@arm.com>>
Cc: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: Running two SimpleDram instances simulataniously

If you want to control the virtual to physical mapping, I am afraid you have to figure out a way to control the page allocation in the OS. Perhaps someone on the list knows a sensible way of achieving this without too much Linux brain surgery.

OS is not required. In my case, I have the list of virtual address which I know that they should always go through DDR3 timing model and the rest of the virtual addresses should go to PCM timing model. In the integrated patch of dramsim2 with GEM5 it was trivial where I added this logic in "DRAMSim2::MemoryPort::recvTimingReq". I instantiated two instances of dramsim2 (one with DDR3 timing and second with PCM timing). Then in recvTimingReq method I was checking the incoming virtual address and then calling appropriate dramsim2 instance accordingly.

I want to do similar thing with SimpleDRAM model of Gem5. Is it possible?

Thanks.

kind Regards, Ahmad




Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Date: Friday, 25 October 2013 11:18
To: Andreas Hansson <***@arm.com<mailto:***@arm.com>>, gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>

Subject: Re: Running two SimpleDram instances simulataniously

Thanks Andreas for the details. As I want to add a logic of which virtual addresses should go to which memory controller (DDR3 or PCM), so I was thinking that I would have one memory port that receives packet from the system and then I add up logic of virtual address and call the appropriate memory controller (DDR3 or PCM) afterwards. Do you suggest the same?

Otherwise if we add two memory controller ports to the memory bus then what place would I add the logic of which virtual address should go to which controller?

CC'ing user list.

Thanks.

Best Regards, Ahmad


On 24 October 2013 19:28, Andreas Hansson <***@arm.com<mailto:***@arm.com>> wrote:
Hi Ahmad,

You can instantiate as many controller as you want, all you have to do is edit the python files. You can either try and add it as an option to fs.py or similar, or manually create a system in a separate .py file.

You can simply do system.ddr3_ctrl = SimpleDDR3() and system.pcm_ctrl = SimplePCM() (you have to create the latter class). You pass the address range as a parameter to each controller. When you connect them to the bus they will automatically be updating the address map in the bus.

Good luck.

As a final note, please stick to the mailing list :-)

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Date: Wednesday, 23 October 2013 20:29
To: Andreas Hansson <***@arm.com<mailto:***@arm.com>>
Subject: Re: Running two SimpleDram instances simulataniously

Or more simply, how would it be possible to use both "SimpleLPDDR2_S4" and "SimpleDDR3" simultaneously. I will redirect some virtual addresses to SimpleLPDDR2_S4 and some to SimpleDDR3.

Thanks.

kind Regards, Ahmad


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Ahmad Hassan
2013-10-28 17:14:09 UTC
Permalink
Hi Andreas,

I am attaching two memory controller to the system as per your advice
system.ddr3_ctl and system.pcm_ctl. I found the following details
inside FSConfig.py

//makeX86System method
self.physmem = SimpleDDR3(range = AddrRange('1GB'))
self.mem_ranges = [self.physmem.range]

//connectX86ClassicSystem method
x86_sys.membus = MemBus()
x86_sys.physmem.port = x86_sys.membus.master
x86_sys.bridge.slave = x86_sys.membus.master
x86_sys.apicbridge.master = x86_sys.membus.slave
x86_sys.system_port = x86_sys.membus.slave


I am new to Gem5 memory model. Please can you give me hints how to change
above initialization to two memory controllers and attach them to the bus.

Thanks.

Best Regards, Ahmad
Hi Ahmad,
You can instantiate as many controller as you want, all you have to do
is edit the python files. You can either try and add it as an option to
fs.py or similar, or manually create a system in a separate .py file.
You can simply do system.ddr3_ctrl = SimpleDDR3() and system.pcm_ctrl =
SimplePCM() (you have to create the latter class). You pass the address
range as a parameter to each controller. When you connect them to the bus
they will automatically be updating the address map in the bus.
Good luck.
As a final note, please stick to the mailing list :-)
Andreas
Date: Wednesday, 23 October 2013 20:29
Subject: Re: Running two SimpleDram instances simulataniously
Or more simply, how would it be possible to use both "SimpleLPDDR2_S4"
and "SimpleDDR3" simultaneously. I will redirect some virtual addresses
to SimpleLPDDR2_S4 and some to SimpleDDR3.
Thanks.
kind Regards, Ahmad
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
Andreas Hansson
2013-10-28 22:50:47 UTC
Permalink
Hi Ahmad,

You will have to decide where to map it in the system memory map, and make sure that range is not occupied. For example:

self.dram_ctrl = SimpleDDR3(range = AddrRange(‘512MB’))
self.pcm_ctrl = SimplePCM(range = AddrRange(start = ‘512MB', size = ‘512MB’))
self.mem_ranges = [self.dram_ctrl.range, self.pcm_ctrl.range]

self.membus.master = self.dram_ctrl.port
self.membus_master = self.pcm_ctrl.port

If you want multi-channel controllers like gets even more complicated. In that case I’d suggest to use the MemConfig convenience functions.

Good luck with the changes.

Andreas


From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Monday, 28 October 2013 18:14
To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously

Hi Andreas,

I am attaching two memory controller to the system as per your advice system.ddr3_ctl and system.pcm_ctl. I found the following details inside FSConfig.py

//makeX86System method
self.physmem = SimpleDDR3(range = AddrRange('1GB'))
self.mem_ranges = [self.physmem.range]

//connectX86ClassicSystem method
x86_sys.membus = MemBus()
x86_sys.physmem.port = x86_sys.membus.master
x86_sys.bridge.slave = x86_sys.membus.master
x86_sys.apicbridge.master = x86_sys.membus.slave
x86_sys.system_port = x86_sys.membus.slave


I am new to Gem5 memory model. Please can you give me hints how to change above initialization to two memory controllers and attach them to the bus.

Thanks.

Best Regards, Ahmad


On 24 October 2013 19:28, Andreas Hansson <***@arm.com<mailto:***@arm.com>> wrote:
Hi Ahmad,

You can instantiate as many controller as you want, all you have to do is edit the python files. You can either try and add it as an option to fs.py or similar, or manually create a system in a separate .py file.

You can simply do system.ddr3_ctrl = SimpleDDR3() and system.pcm_ctrl = SimplePCM() (you have to create the latter class). You pass the address range as a parameter to each controller. When you connect them to the bus they will automatically be updating the address map in the bus.

Good luck.

As a final note, please stick to the mailing list :-)

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Date: Wednesday, 23 October 2013 20:29
To: Andreas Hansson <***@arm.com<mailto:***@arm.com>>
Subject: Re: Running two SimpleDram instances simulataniously

Or more simply, how would it be possible to use both "SimpleLPDDR2_S4" and "SimpleDDR3" simultaneously. I will redirect some virtual addresses to SimpleLPDDR2_S4 and some to SimpleDDR3.

Thanks.

kind Regards, Ahmad


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Ahmad Hassan
2013-10-29 17:26:38 UTC
Permalink
Hi Andreas,

Thanks. The following worked fine:

self.dram_ctl = SimpleDDR3(range = AddrRange('1GB'))
self.pcm_ctl = SimplePCM(range = AddrRange(start='1GB', size='1GB'))
self.mem_ranges = [self.dram_ctl.range, self.pcm_ctl.range]
x86_sys.dram_ctl.port = x86_sys.membus.master
x86_sys.pcm_ctl.port = x86_sys.membus.master

If I change findPorts in the base Bus to redirect the packets to port
dram_ctl or pcm_ctl based on virtual address then I get assertion error
because physical memory ranges of both memory controllers are different

gem5.opt: build/X86/mem/abstract_mem.cc:307: void
AbstractMemory::access(PacketPtr): Assertion `AddrRange(pkt->getAddr(),
pkt->getAddr() + pkt->getSize() - 1).isSubset(range)' failed.
Program aborted at cycle 0

Please can you advise on How to avoid/hack above assertion failure if the
memory packets are being redirected based on virtual address.

Thanks.

--Ahmad
Hi Ahmad,
You will have to decide where to map it in the system memory map, and
self.dram_ctrl = SimpleDDR3(range = AddrRange(‘512MB’))
self.pcm_ctrl = SimplePCM(range = AddrRange(start = ‘512MB', size = ‘512MB’))
self.mem_ranges = [self.dram_ctrl.range, self.pcm_ctrl.range]
self.membus.master = self.dram_ctrl.port
self.membus_master = self.pcm_ctrl.port
If you want multi-channel controllers like gets even more complicated.
In that case I’d suggest to use the MemConfig convenience functions.
Good luck with the changes.
Andreas
Date: Monday, 28 October 2013 18:14
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously
Hi Andreas,
I am attaching two memory controller to the system as per your advice
system.ddr3_ctl and system.pcm_ctl. I found the following details
inside FSConfig.py
//makeX86System method
self.physmem = SimpleDDR3(range = AddrRange('1GB'))
self.mem_ranges = [self.physmem.range]
//connectX86ClassicSystem method
x86_sys.membus = MemBus()
x86_sys.physmem.port = x86_sys.membus.master
x86_sys.bridge.slave = x86_sys.membus.master
x86_sys.apicbridge.master = x86_sys.membus.slave
x86_sys.system_port = x86_sys.membus.slave
I am new to Gem5 memory model. Please can you give me hints how to
change above initialization to two memory controllers and attach them to
the bus.
Thanks.
Best Regards, Ahmad
Hi Ahmad,
You can instantiate as many controller as you want, all you have to do
is edit the python files. You can either try and add it as an option to
fs.py or similar, or manually create a system in a separate .py file.
You can simply do system.ddr3_ctrl = SimpleDDR3() and system.pcm_ctrl =
SimplePCM() (you have to create the latter class). You pass the address
range as a parameter to each controller. When you connect them to the bus
they will automatically be updating the address map in the bus.
Good luck.
As a final note, please stick to the mailing list :-)
Andreas
Date: Wednesday, 23 October 2013 20:29
Subject: Re: Running two SimpleDram instances simulataniously
Or more simply, how would it be possible to use both "SimpleLPDDR2_S4"
and "SimpleDDR3" simultaneously. I will redirect some virtual addresses
to SimpleLPDDR2_S4 and some to SimpleDDR3.
Thanks.
kind Regards, Ahmad
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
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Ahmad Hassan
2013-10-31 16:12:19 UTC
Permalink
HI Andreas,

I have connected two memory controllers and I can see the following two
port IDs and their physical address ranges:

Adding range [0 : 2147483647] for id 0 system.membus // 2GB memory
Adding range [2147483648 : 3221225471] for id 1 system.membus //1GB
memroy

Inside findPort method of bus.cc, if I assign the packet of port id '0' to
port id '1' then I get the following assertion error. This happens in half
way through the linux boot up:

gem5.opt: build/X86/dev/x86/cmos.cc:70: virtual Tick
X86ISA::Cmos::write(PacketPtr): Assertion `pkt->getSize() == 1' failed.

Please do you know what is causing that? Also I had to disable assertion
in abstract memory which validates that the packet's physical address in
with in the range of memory controller.

Thanks.

kind Regards, Ahmad
Andreas Hansson
2013-10-31 16:25:45 UTC
Permalink
Hi Ahmad,

I could be wrong, but judging by your mail, I get the impression that you’re overriding the address decoding. That is essentially saying “If I send requests for address X to address Y, why do things not work?”. I would be very surprised if it did, as two addresses will now map to the same location :-). Perhaps I’m not understanding what you’ve changed.

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Thursday, 31 October 2013 16:12
To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously

HI Andreas,

I have connected two memory controllers and I can see the following two port IDs and their physical address ranges:

Adding range [0 : 2147483647] for id 0 system.membus // 2GB memory
Adding range [2147483648 : 3221225471] for id 1 system.membus //1GB memroy

Inside findPort method of bus.cc, if I assign the packet of port id '0' to port id '1' then I get the following assertion error. This happens in half way through the linux boot up:

gem5.opt: build/X86/dev/x86/cmos.cc:70: virtual Tick X86ISA::Cmos::write(PacketPtr): Assertion `pkt->getSize() == 1' failed.

Please do you know what is causing that? Also I had to disable assertion in abstract memory which validates that the packet's physical address in with in the range of memory controller.

Thanks.

kind Regards, Ahmad

-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Ahmad Hassan
2013-10-31 16:51:31 UTC
Permalink
Hi Andreas,

In my system:
DDR3 memory controller: Port ID 0 //2GB capacity
DDR2 memory controller: Port ID 1 //1GB capacity

So I want to do the following:

When the packet comes into bus.cc:findPort then it searches for packet's
physical address in the registered portMap of address ranges and returns
the appropriate port ID. I don't want to do this. Instead, I want to select
port based on the virtual address. I have list of virtual addresses say
V=[V1....Vn] and I want to redirect all the packets with virtual address
within set 'V' to DDR3 Port 0 and all other memory packets to the DDR2 port
1.

In order to achieve this, I changed bus.cc:findPort as:

if (search(V, pkt->req->getVaddr()) == true)
dest_id = 0;
else
dest_id = 1;

After that, abstract_mem.cc:access complained that the packet address
doesn't belong to the range of PORT '1'. Just as a quick hack, I changed it
as:

old: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
new: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - 0; // Port ID 0
range starts with '0'

Now the linux starts booting but during the half way, it throws this cmos
assertion. Please can you suggest the clean or right way of implementing
what I am trying to achieve.

Thanks a lot

kind Regards, Ahmad
Hi Ahmad,
I could be wrong, but judging by your mail, I get the impression that
you’re overriding the address decoding. That is essentially saying “If I
send requests for address X to address Y, why do things not work?”. I would
be very surprised if it did, as two addresses will now map to the same
location :-). Perhaps I’m not understanding what you’ve changed.
Andreas
Date: Thursday, 31 October 2013 16:12
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously
HI Andreas,
I have connected two memory controllers and I can see the following two
Adding range [0 : 2147483647] for id 0 system.membus // 2GB memory
Adding range [2147483648 : 3221225471] for id 1 system.membus
//1GB memroy
Inside findPort method of bus.cc, if I assign the packet of port id '0'
to port id '1' then I get the following assertion error. This happens in
gem5.opt: build/X86/dev/x86/cmos.cc:70: virtual Tick
X86ISA::Cmos::write(PacketPtr): Assertion `pkt->getSize() == 1' failed.
Please do you know what is causing that? Also I had to disable
assertion in abstract memory which validates that the packet's physical
address in with in the range of memory controller.
Thanks.
kind Regards, Ahmad
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Andreas Hansson
2013-10-31 18:00:00 UTC
Permalink
Hi Ahmad,

If you change the bus code then every bus in the system will do this, including the I/O bus. I suspect this is the reason for your error. You can keep on the hackish path and add a name check to only do this for the membus (or add a parameter to the bus and change the MemBus instance), or preferably get of the hackish path and rely on physical addresses and sort out your “placement” by assigning the appropriate physical addresses in your TLBs (or preferably in the OS).

Red pill or blue pill.

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Thursday, 31 October 2013 16:51
To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously

Hi Andreas,

In my system:
DDR3 memory controller: Port ID 0 //2GB capacity
DDR2 memory controller: Port ID 1 //1GB capacity

So I want to do the following:

When the packet comes into bus.cc:findPort then it searches for packet's physical address in the registered portMap of address ranges and returns the appropriate port ID. I don't want to do this. Instead, I want to select port based on the virtual address. I have list of virtual addresses say V=[V1....Vn] and I want to redirect all the packets with virtual address within set 'V' to DDR3 Port 0 and all other memory packets to the DDR2 port 1.

In order to achieve this, I changed bus.cc:findPort as:

if (search(V, pkt->req->getVaddr()) == true)
dest_id = 0;
else
dest_id = 1;

After that, abstract_mem.cc:access complained that the packet address doesn't belong to the range of PORT '1'. Just as a quick hack, I changed it as:

old: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
new: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - 0; // Port ID 0 range starts with '0'

Now the linux starts booting but during the half way, it throws this cmos assertion. Please can you suggest the clean or right way of implementing what I am trying to achieve.

Thanks a lot

kind Regards, Ahmad


On 31 October 2013 16:25, Andreas Hansson <***@arm.com<mailto:***@arm.com>> wrote:
Hi Ahmad,

I could be wrong, but judging by your mail, I get the impression that you’re overriding the address decoding. That is essentially saying “If I send requests for address X to address Y, why do things not work?”. I would be very surprised if it did, as two addresses will now map to the same location :-). Perhaps I’m not understanding what you’ve changed.

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Thursday, 31 October 2013 16:12

To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously

HI Andreas,

I have connected two memory controllers and I can see the following two port IDs and their physical address ranges:

Adding range [0 : 2147483647] for id 0 system.membus // 2GB memory
Adding range [2147483648 : 3221225471] for id 1 system.membus //1GB memroy

Inside findPort method of bus.cc, if I assign the packet of port id '0' to port id '1' then I get the following assertion error. This happens in half way through the linux boot up:

gem5.opt: build/X86/dev/x86/cmos.cc:70: virtual Tick X86ISA::Cmos::write(PacketPtr): Assertion `pkt->getSize() == 1' failed.

Please do you know what is causing that? Also I had to disable assertion in abstract memory which validates that the packet's physical address in with in the range of memory controller.

Thanks.

kind Regards, Ahmad

-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782

_______________________________________________
gem5-users mailing list
gem5-***@gem5.org<mailto:gem5-***@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Ahmad Hassan
2013-11-28 13:43:26 UTC
Permalink
Hi Andreas,

I have defined two memory controllers:

self.dram2_ctl = SimpleDDR3(range = AddrRange(start='0MB',size='3GB'))
self.dram1_ctl = SimpleDDR3(range = AddrRange(start='10GB',size='16GB'))

But I am getting exception in findPort method where it raises because it
tries to access physical address 6438256672 for membus

DPRINTF(BusAddrRanges, "Unable to find destination for addr %#llx, "
"will use default port\n", addr);

As a result of that, I get segmentation fault during memcpy operation in
abstract_mem.cc:access
This error is happening because system is assuming that all the 19GB of
physical memory is contiguous. Please can you advise me how to fix this.
Thanks.

Best Regards, Hassan
Hi Ahmad,
If you change the bus code then every bus in the system will do this,
including the I/O bus. I suspect this is the reason for your error. You can
keep on the hackish path and add a name check to only do this for the
membus (or add a parameter to the bus and change the MemBus instance), or
preferably get of the hackish path and rely on physical addresses and sort
out your “placement” by assigning the appropriate physical addresses in
your TLBs (or preferably in the OS).
Red pill or blue pill.
Andreas
Date: Thursday, 31 October 2013 16:51
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously
Hi Andreas,
DDR3 memory controller: Port ID 0 //2GB capacity
DDR2 memory controller: Port ID 1 //1GB capacity
When the packet comes into bus.cc:findPort then it searches for
packet's physical address in the registered portMap of address ranges and
returns the appropriate port ID. I don't want to do this. Instead, I want
to select port based on the virtual address. I have list of virtual
addresses say V=[V1....Vn] and I want to redirect all the packets with
virtual address within set 'V' to DDR3 Port 0 and all other memory packets
to the DDR2 port 1.
if (search(V, pkt->req->getVaddr()) == true)
dest_id = 0;
else
dest_id = 1;
After that, abstract_mem.cc:access complained that the packet address
doesn't belong to the range of PORT '1'. Just as a quick hack, I changed it
old: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
new: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - 0; // Port ID 0
range starts with '0'
Now the linux starts booting but during the half way, it throws this
cmos assertion. Please can you suggest the clean or right way of
implementing what I am trying to achieve.
Thanks a lot
kind Regards, Ahmad
Hi Ahmad,
I could be wrong, but judging by your mail, I get the impression that
you’re overriding the address decoding. That is essentially saying “If I
send requests for address X to address Y, why do things not work?”. I would
be very surprised if it did, as two addresses will now map to the same
location :-). Perhaps I’m not understanding what you’ve changed.
Andreas
Date: Thursday, 31 October 2013 16:12
Subject: Re: [gem5-users] Running two SimpleDram instances
simulataniously
HI Andreas,
I have connected two memory controllers and I can see the following two
Adding range [0 : 2147483647] for id 0 system.membus // 2GB memory
Adding range [2147483648 : 3221225471] for id 1 system.membus
//1GB memroy
Inside findPort method of bus.cc, if I assign the packet of port id '0'
to port id '1' then I get the following assertion error. This happens in
gem5.opt: build/X86/dev/x86/cmos.cc:70: virtual Tick
X86ISA::Cmos::write(PacketPtr): Assertion `pkt->getSize() == 1' failed.
Please do you know what is causing that? Also I had to disable
assertion in abstract memory which validates that the packet's physical
address in with in the range of memory controller.
Thanks.
kind Regards, Ahmad
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Andreas Hansson
2013-11-28 13:53:07 UTC
Permalink
Hi Hassan,

What is it that is assuming that the memory is contiguous? The guest OS?

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Thursday, 28 November 2013 06:43
To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously

Hi Andreas,

I have defined two memory controllers:

self.dram2_ctl = SimpleDDR3(range = AddrRange(start='0MB',size='3GB'))
self.dram1_ctl = SimpleDDR3(range = AddrRange(start='10GB',size='16GB'))

But I am getting exception in findPort method where it raises because it tries to access physical address 6438256672 for membus

DPRINTF(BusAddrRanges, "Unable to find destination for addr %#llx, "
"will use default port\n", addr);

As a result of that, I get segmentation fault during memcpy operation in abstract_mem.cc:access
This error is happening because system is assuming that all the 19GB of physical memory is contiguous. Please can you advise me how to fix this. Thanks.

Best Regards, Hassan



On 31 October 2013 18:00, Andreas Hansson <***@arm.com<mailto:***@arm.com>> wrote:
Hi Ahmad,

If you change the bus code then every bus in the system will do this, including the I/O bus. I suspect this is the reason for your error. You can keep on the hackish path and add a name check to only do this for the membus (or add a parameter to the bus and change the MemBus instance), or preferably get of the hackish path and rely on physical addresses and sort out your “placement” by assigning the appropriate physical addresses in your TLBs (or preferably in the OS).

Red pill or blue pill.

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Thursday, 31 October 2013 16:51

To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously

Hi Andreas,

In my system:
DDR3 memory controller: Port ID 0 //2GB capacity
DDR2 memory controller: Port ID 1 //1GB capacity

So I want to do the following:

When the packet comes into bus.cc:findPort then it searches for packet's physical address in the registered portMap of address ranges and returns the appropriate port ID. I don't want to do this. Instead, I want to select port based on the virtual address. I have list of virtual addresses say V=[V1....Vn] and I want to redirect all the packets with virtual address within set 'V' to DDR3 Port 0 and all other memory packets to the DDR2 port 1.

In order to achieve this, I changed bus.cc:findPort as:

if (search(V, pkt->req->getVaddr()) == true)
dest_id = 0;
else
dest_id = 1;

After that, abstract_mem.cc:access complained that the packet address doesn't belong to the range of PORT '1'. Just as a quick hack, I changed it as:

old: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
new: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - 0; // Port ID 0 range starts with '0'

Now the linux starts booting but during the half way, it throws this cmos assertion. Please can you suggest the clean or right way of implementing what I am trying to achieve.

Thanks a lot

kind Regards, Ahmad


On 31 October 2013 16:25, Andreas Hansson <***@arm.com<mailto:***@arm.com>> wrote:
Hi Ahmad,

I could be wrong, but judging by your mail, I get the impression that you’re overriding the address decoding. That is essentially saying “If I send requests for address X to address Y, why do things not work?”. I would be very surprised if it did, as two addresses will now map to the same location :-). Perhaps I’m not understanding what you’ve changed.

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Thursday, 31 October 2013 16:12

To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously

HI Andreas,

I have connected two memory controllers and I can see the following two port IDs and their physical address ranges:

Adding range [0 : 2147483647] for id 0 system.membus // 2GB memory
Adding range [2147483648 : 3221225471] for id 1 system.membus //1GB memroy

Inside findPort method of bus.cc, if I assign the packet of port id '0' to port id '1' then I get the following assertion error. This happens in half way through the linux boot up:

gem5.opt: build/X86/dev/x86/cmos.cc:70: virtual Tick X86ISA::Cmos::write(PacketPtr): Assertion `pkt->getSize() == 1' failed.

Please do you know what is causing that? Also I had to disable assertion in abstract memory which validates that the packet's physical address in with in the range of memory controller.

Thanks.

kind Regards, Ahmad

-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782

_______________________________________________
gem5-users mailing list
gem5-***@gem5.org<mailto:gem5-***@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782

_______________________________________________
gem5-users mailing list
gem5-***@gem5.org<mailto:gem5-***@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Ahmad Hassan
2013-11-28 14:50:45 UTC
Permalink
Hi Andreas,

I assume so. I get this 'segmentation fault' while booting
linux: ./build/X86/gem5.opt configs/example/fs.py
--kernel=x86_64-vmlinux-2.6.22.9.smp

But I think, I booted the linux last week with similar configuration and I
think it worked fine. It seems bit strange to me that I am seeing this
segmentation fault now.

Best Regards, Hassan
Post by Andreas Hansson
Hi Hassan,
What is it that is assuming that the memory is contiguous? The guest OS?
Andreas
Date: Thursday, 28 November 2013 06:43
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously
Hi Andreas,
self.dram2_ctl = SimpleDDR3(range =
AddrRange(start='0MB',size='3GB'))
self.dram1_ctl = SimpleDDR3(range =
AddrRange(start='10GB',size='16GB'))
But I am getting exception in findPort method where it raises because it
tries to access physical address 6438256672 for membus
DPRINTF(BusAddrRanges, "Unable to find destination for addr %#llx, "
"will use default port\n", addr);
As a result of that, I get segmentation fault during memcpy operation in
abstract_mem.cc:access
This error is happening because system is assuming that all the 19GB of
physical memory is contiguous. Please can you advise me how to fix this.
Thanks.
Best Regards, Hassan
Hi Ahmad,
If you change the bus code then every bus in the system will do this,
including the I/O bus. I suspect this is the reason for your error. You can
keep on the hackish path and add a name check to only do this for the
membus (or add a parameter to the bus and change the MemBus instance), or
preferably get of the hackish path and rely on physical addresses and sort
out your “placement” by assigning the appropriate physical addresses in
your TLBs (or preferably in the OS).
Red pill or blue pill.
Andreas
Date: Thursday, 31 October 2013 16:51
Subject: Re: [gem5-users] Running two SimpleDram instances
simulataniously
Hi Andreas,
DDR3 memory controller: Port ID 0 //2GB capacity
DDR2 memory controller: Port ID 1 //1GB capacity
When the packet comes into bus.cc:findPort then it searches for
packet's physical address in the registered portMap of address ranges and
returns the appropriate port ID. I don't want to do this. Instead, I want
to select port based on the virtual address. I have list of virtual
addresses say V=[V1....Vn] and I want to redirect all the packets with
virtual address within set 'V' to DDR3 Port 0 and all other memory packets
to the DDR2 port 1.
if (search(V, pkt->req->getVaddr()) == true)
dest_id = 0;
else
dest_id = 1;
After that, abstract_mem.cc:access complained that the packet address
doesn't belong to the range of PORT '1'. Just as a quick hack, I changed it
old: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
new: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - 0; // Port ID 0
range starts with '0'
Now the linux starts booting but during the half way, it throws this
cmos assertion. Please can you suggest the clean or right way of
implementing what I am trying to achieve.
Thanks a lot
kind Regards, Ahmad
Hi Ahmad,
I could be wrong, but judging by your mail, I get the impression that
you’re overriding the address decoding. That is essentially saying “If I
send requests for address X to address Y, why do things not work?”. I would
be very surprised if it did, as two addresses will now map to the same
location :-). Perhaps I’m not understanding what you’ve changed.
Andreas
Date: Thursday, 31 October 2013 16:12
Subject: Re: [gem5-users] Running two SimpleDram instances
simulataniously
HI Andreas,
I have connected two memory controllers and I can see the following
Adding range [0 : 2147483647] for id 0 system.membus // 2GB memory
Adding range [2147483648 : 3221225471] for id 1 system.membus
//1GB memroy
Inside findPort method of bus.cc, if I assign the packet of port id
'0' to port id '1' then I get the following assertion error. This happens
gem5.opt: build/X86/dev/x86/cmos.cc:70: virtual Tick
X86ISA::Cmos::write(PacketPtr): Assertion `pkt->getSize() == 1' failed.
Please do you know what is causing that? Also I had to disable
assertion in abstract memory which validates that the packet's physical
address in with in the range of memory controller.
Thanks.
kind Regards, Ahmad
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1
9NJ, Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Ahmad Hassan
2013-11-28 15:55:04 UTC
Permalink
Hi Andreas,

To make sure it is not caused by my local changes, I just cloned the fresh
revison 9644:07352f119e48 and defined two memory controllers as:

self.physmem = SimpleDDR3(range = AddrRange(start="0GB", size="2GB"))
self.physmem2 = SimpleDDR3(range = AddrRange(start="50GB",size="1GB"))
self.mem_ranges = [self.physmem.range,self.physmem2.range]

Again, I see the same error where linux boot-up fails while accessing
physical address: 3217031168. It seems that guest OS assumes that All 3GB
space is contiguous.

I don't know why it worked last week.

Thanks for the help.

Best Regards, Hassan
Post by Ahmad Hassan
Hi Andreas,
I assume so. I get this 'segmentation fault' while booting
linux: ./build/X86/gem5.opt configs/example/fs.py
--kernel=x86_64-vmlinux-2.6.22.9.smp
But I think, I booted the linux last week with similar configuration and I
think it worked fine. It seems bit strange to me that I am seeing this
segmentation fault now.
Best Regards, Hassan
Post by Andreas Hansson
Hi Hassan,
What is it that is assuming that the memory is contiguous? The guest OS?
Andreas
Date: Thursday, 28 November 2013 06:43
Subject: Re: [gem5-users] Running two SimpleDram instances
simulataniously
Hi Andreas,
self.dram2_ctl = SimpleDDR3(range =
AddrRange(start='0MB',size='3GB'))
self.dram1_ctl = SimpleDDR3(range =
AddrRange(start='10GB',size='16GB'))
But I am getting exception in findPort method where it raises because
it tries to access physical address 6438256672 for membus
DPRINTF(BusAddrRanges, "Unable to find destination for addr %#llx, "
"will use default port\n", addr);
As a result of that, I get segmentation fault during memcpy operation
in abstract_mem.cc:access
This error is happening because system is assuming that all the 19GB of
physical memory is contiguous. Please can you advise me how to fix this.
Thanks.
Best Regards, Hassan
Hi Ahmad,
If you change the bus code then every bus in the system will do this,
including the I/O bus. I suspect this is the reason for your error. You can
keep on the hackish path and add a name check to only do this for the
membus (or add a parameter to the bus and change the MemBus instance), or
preferably get of the hackish path and rely on physical addresses and sort
out your “placement” by assigning the appropriate physical addresses in
your TLBs (or preferably in the OS).
Red pill or blue pill.
Andreas
Date: Thursday, 31 October 2013 16:51
Subject: Re: [gem5-users] Running two SimpleDram instances
simulataniously
Hi Andreas,
DDR3 memory controller: Port ID 0 //2GB capacity
DDR2 memory controller: Port ID 1 //1GB capacity
When the packet comes into bus.cc:findPort then it searches for
packet's physical address in the registered portMap of address ranges and
returns the appropriate port ID. I don't want to do this. Instead, I want
to select port based on the virtual address. I have list of virtual
addresses say V=[V1....Vn] and I want to redirect all the packets with
virtual address within set 'V' to DDR3 Port 0 and all other memory packets
to the DDR2 port 1.
if (search(V, pkt->req->getVaddr()) == true)
dest_id = 0;
else
dest_id = 1;
After that, abstract_mem.cc:access complained that the packet address
doesn't belong to the range of PORT '1'. Just as a quick hack, I changed it
old: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
new: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - 0; // Port ID 0
range starts with '0'
Now the linux starts booting but during the half way, it throws this
cmos assertion. Please can you suggest the clean or right way of
implementing what I am trying to achieve.
Thanks a lot
kind Regards, Ahmad
Hi Ahmad,
I could be wrong, but judging by your mail, I get the impression that
you’re overriding the address decoding. That is essentially saying “If I
send requests for address X to address Y, why do things not work?”. I would
be very surprised if it did, as two addresses will now map to the same
location :-). Perhaps I’m not understanding what you’ve changed.
Andreas
Date: Thursday, 31 October 2013 16:12
Subject: Re: [gem5-users] Running two SimpleDram instances
simulataniously
HI Andreas,
I have connected two memory controllers and I can see the following
Adding range [0 : 2147483647] for id 0 system.membus // 2GB memory
Adding range [2147483648 : 3221225471] for id 1 system.membus
//1GB memroy
Inside findPort method of bus.cc, if I assign the packet of port id
'0' to port id '1' then I get the following assertion error. This happens
gem5.opt: build/X86/dev/x86/cmos.cc:70: virtual Tick
X86ISA::Cmos::write(PacketPtr): Assertion `pkt->getSize() == 1' failed.
Please do you know what is causing that? Also I had to disable
assertion in abstract memory which validates that the packet's physical
address in with in the range of memory controller.
Thanks.
kind Regards, Ahmad
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information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1
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information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1
9NJ, Registered in England & Wales, Company No: 2548782
_______________________________________________
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confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
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Ahmad Hassan
2013-12-02 16:18:59 UTC
Permalink
Hi Andreas,

Please may I ask if you are experiencing the similar errors if you define a
second main memory controller beyond IO physical address ranges? Would this
be happening or this is completely an undesired behavior?

If Linux always need contiguous physical address range for multiple memory
controllers then is it possible to move IO address range from 3GB start
address to something 128GB starting address and then define two main memory
controllers that share the physical address range of 0GB to 128GB to have
128 GB RAM capacity please?

In another attempt, I tried to move the first main memory controller
starting from 0GB to 10GB but it doesn't work because linux is accessing
memory between 0 to 128MB address range.

Thanks again for your help.

Best Regards, Hassan
Post by Ahmad Hassan
Hi Andreas,
To make sure it is not caused by my local changes, I just cloned the fresh
self.physmem = SimpleDDR3(range = AddrRange(start="0GB", size="2GB"))
self.physmem2 = SimpleDDR3(range = AddrRange(start="50GB",size="1GB"))
self.mem_ranges = [self.physmem.range,self.physmem2.range]
Again, I see the same error where linux boot-up fails while accessing
physical address: 3217031168. It seems that guest OS assumes that All 3GB
space is contiguous.
I don't know why it worked last week.
Thanks for the help.
Best Regards, Hassan
Post by Ahmad Hassan
Hi Andreas,
I assume so. I get this 'segmentation fault' while booting
linux: ./build/X86/gem5.opt configs/example/fs.py
--kernel=x86_64-vmlinux-2.6.22.9.smp
But I think, I booted the linux last week with similar configuration and
I think it worked fine. It seems bit strange to me that I am seeing this
segmentation fault now.
Best Regards, Hassan
Post by Andreas Hansson
Hi Hassan,
What is it that is assuming that the memory is contiguous? The guest OS?
Andreas
Date: Thursday, 28 November 2013 06:43
Subject: Re: [gem5-users] Running two SimpleDram instances
simulataniously
Hi Andreas,
self.dram2_ctl = SimpleDDR3(range =
AddrRange(start='0MB',size='3GB'))
self.dram1_ctl = SimpleDDR3(range =
AddrRange(start='10GB',size='16GB'))
But I am getting exception in findPort method where it raises because
it tries to access physical address 6438256672 for membus
DPRINTF(BusAddrRanges, "Unable to find destination for addr %#llx, "
"will use default port\n", addr);
As a result of that, I get segmentation fault during memcpy operation
in abstract_mem.cc:access
This error is happening because system is assuming that all the 19GB of
physical memory is contiguous. Please can you advise me how to fix this.
Thanks.
Best Regards, Hassan
Hi Ahmad,
If you change the bus code then every bus in the system will do this,
including the I/O bus. I suspect this is the reason for your error. You can
keep on the hackish path and add a name check to only do this for the
membus (or add a parameter to the bus and change the MemBus instance), or
preferably get of the hackish path and rely on physical addresses and sort
out your “placement” by assigning the appropriate physical addresses in
your TLBs (or preferably in the OS).
Red pill or blue pill.
Andreas
Date: Thursday, 31 October 2013 16:51
Subject: Re: [gem5-users] Running two SimpleDram instances
simulataniously
Hi Andreas,
DDR3 memory controller: Port ID 0 //2GB capacity
DDR2 memory controller: Port ID 1 //1GB capacity
When the packet comes into bus.cc:findPort then it searches for
packet's physical address in the registered portMap of address ranges and
returns the appropriate port ID. I don't want to do this. Instead, I want
to select port based on the virtual address. I have list of virtual
addresses say V=[V1....Vn] and I want to redirect all the packets with
virtual address within set 'V' to DDR3 Port 0 and all other memory packets
to the DDR2 port 1.
if (search(V, pkt->req->getVaddr()) == true)
dest_id = 0;
else
dest_id = 1;
After that, abstract_mem.cc:access complained that the packet address
doesn't belong to the range of PORT '1'. Just as a quick hack, I changed it
old: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
new: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - 0; // Port ID 0
range starts with '0'
Now the linux starts booting but during the half way, it throws this
cmos assertion. Please can you suggest the clean or right way of
implementing what I am trying to achieve.
Thanks a lot
kind Regards, Ahmad
Hi Ahmad,
I could be wrong, but judging by your mail, I get the impression
that you’re overriding the address decoding. That is essentially saying “If
I send requests for address X to address Y, why do things not work?”. I
would be very surprised if it did, as two addresses will now map to the
same location :-). Perhaps I’m not understanding what you’ve changed.
Andreas
Date: Thursday, 31 October 2013 16:12
Subject: Re: [gem5-users] Running two SimpleDram instances
simulataniously
HI Andreas,
I have connected two memory controllers and I can see the following
Adding range [0 : 2147483647] for id 0 system.membus // 2GB memory
Adding range [2147483648 : 3221225471] for id 1 system.membus
//1GB memroy
Inside findPort method of bus.cc, if I assign the packet of port id
'0' to port id '1' then I get the following assertion error. This happens
gem5.opt: build/X86/dev/x86/cmos.cc:70: virtual Tick
X86ISA::Cmos::write(PacketPtr): Assertion `pkt->getSize() == 1' failed.
Please do you know what is causing that? Also I had to disable
assertion in abstract memory which validates that the packet's physical
address in with in the range of memory controller.
Thanks.
kind Regards, Ahmad
-- IMPORTANT NOTICE: The contents of this email and any attachments
are confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1
9NJ, Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1
9NJ, Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1
9NJ, Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
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Andreas Hansson
2013-12-02 17:37:24 UTC
Permalink
Hi Hassan,

Someone skilled in the assumptions of x86 memory layout may be able to help you. I doubt there is an easy fix, but I could be wrong.

For ARM it should not be a problem to have this “segmented” memory. Currently the gem5 ARM Linux System assumes a single range presented to the OS, but this could easily be fixed (see LinuxArmSystem::initState). If you take the plunge and go this route please share the patch on RB.

Thanks,

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Monday, 2 December 2013 16:18
To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously

Hi Andreas,

Please may I ask if you are experiencing the similar errors if you define a second main memory controller beyond IO physical address ranges? Would this be happening or this is completely an undesired behavior?

If Linux always need contiguous physical address range for multiple memory controllers then is it possible to move IO address range from 3GB start address to something 128GB starting address and then define two main memory controllers that share the physical address range of 0GB to 128GB to have 128 GB RAM capacity please?

In another attempt, I tried to move the first main memory controller starting from 0GB to 10GB but it doesn't work because linux is accessing memory between 0 to 128MB address range.

Thanks again for your help.

Best Regards, Hassan



On 28 November 2013 15:55, Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>> wrote:
Hi Andreas,

To make sure it is not caused by my local changes, I just cloned the fresh revison 9644:07352f119e48 and defined two memory controllers as:

self.physmem = SimpleDDR3(range = AddrRange(start="0GB", size="2GB"))
self.physmem2 = SimpleDDR3(range = AddrRange(start="50GB",size="1GB"))
self.mem_ranges = [self.physmem.range,self.physmem2.range]

Again, I see the same error where linux boot-up fails while accessing physical address: 3217031168. It seems that guest OS assumes that All 3GB space is contiguous.

I don't know why it worked last week.

Thanks for the help.

Best Regards, Hassan



On 28 November 2013 14:50, Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>> wrote:
Hi Andreas,

I assume so. I get this 'segmentation fault' while booting linux: ./build/X86/gem5.opt configs/example/fs.py --kernel=x86_64-vmlinux-2.6.22.9.smp

But I think, I booted the linux last week with similar configuration and I think it worked fine. It seems bit strange to me that I am seeing this segmentation fault now.

Best Regards, Hassan


On 28 November 2013 13:53, Andreas Hansson <***@arm.com<mailto:***@arm.com>> wrote:
Hi Hassan,

What is it that is assuming that the memory is contiguous? The guest OS?

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Thursday, 28 November 2013 06:43

To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously

Hi Andreas,

I have defined two memory controllers:

self.dram2_ctl = SimpleDDR3(range = AddrRange(start='0MB',size='3GB'))
self.dram1_ctl = SimpleDDR3(range = AddrRange(start='10GB',size='16GB'))

But I am getting exception in findPort method where it raises because it tries to access physical address 6438256672 for membus

DPRINTF(BusAddrRanges, "Unable to find destination for addr %#llx, "
"will use default port\n", addr);

As a result of that, I get segmentation fault during memcpy operation in abstract_mem.cc:access
This error is happening because system is assuming that all the 19GB of physical memory is contiguous. Please can you advise me how to fix this. Thanks.

Best Regards, Hassan



On 31 October 2013 18:00, Andreas Hansson <***@arm.com<mailto:***@arm.com>> wrote:
Hi Ahmad,

If you change the bus code then every bus in the system will do this, including the I/O bus. I suspect this is the reason for your error. You can keep on the hackish path and add a name check to only do this for the membus (or add a parameter to the bus and change the MemBus instance), or preferably get of the hackish path and rely on physical addresses and sort out your “placement” by assigning the appropriate physical addresses in your TLBs (or preferably in the OS).

Red pill or blue pill.

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Thursday, 31 October 2013 16:51

To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously

Hi Andreas,

In my system:
DDR3 memory controller: Port ID 0 //2GB capacity
DDR2 memory controller: Port ID 1 //1GB capacity

So I want to do the following:

When the packet comes into bus.cc:findPort then it searches for packet's physical address in the registered portMap of address ranges and returns the appropriate port ID. I don't want to do this. Instead, I want to select port based on the virtual address. I have list of virtual addresses say V=[V1....Vn] and I want to redirect all the packets with virtual address within set 'V' to DDR3 Port 0 and all other memory packets to the DDR2 port 1.

In order to achieve this, I changed bus.cc:findPort as:

if (search(V, pkt->req->getVaddr()) == true)
dest_id = 0;
else
dest_id = 1;

After that, abstract_mem.cc:access complained that the packet address doesn't belong to the range of PORT '1'. Just as a quick hack, I changed it as:

old: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
new: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - 0; // Port ID 0 range starts with '0'

Now the linux starts booting but during the half way, it throws this cmos assertion. Please can you suggest the clean or right way of implementing what I am trying to achieve.

Thanks a lot

kind Regards, Ahmad


On 31 October 2013 16:25, Andreas Hansson <***@arm.com<mailto:***@arm.com>> wrote:
Hi Ahmad,

I could be wrong, but judging by your mail, I get the impression that you’re overriding the address decoding. That is essentially saying “If I send requests for address X to address Y, why do things not work?”. I would be very surprised if it did, as two addresses will now map to the same location :-). Perhaps I’m not understanding what you’ve changed.

Andreas

From: Ahmad Hassan <***@gmail.com<mailto:***@gmail.com>>
Reply-To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Date: Thursday, 31 October 2013 16:12

To: gem5 users mailing list <gem5-***@gem5.org<mailto:gem5-***@gem5.org>>
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously

HI Andreas,

I have connected two memory controllers and I can see the following two port IDs and their physical address ranges:

Adding range [0 : 2147483647] for id 0 system.membus // 2GB memory
Adding range [2147483648 : 3221225471] for id 1 system.membus //1GB memroy

Inside findPort method of bus.cc, if I assign the packet of port id '0' to port id '1' then I get the following assertion error. This happens in half way through the linux boot up:

gem5.opt: build/X86/dev/x86/cmos.cc:70: virtual Tick X86ISA::Cmos::write(PacketPtr): Assertion `pkt->getSize() == 1' failed.

Please do you know what is causing that? Also I had to disable assertion in abstract memory which validates that the packet's physical address in with in the range of memory controller.

Thanks.

kind Regards, Ahmad

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ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782

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ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
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-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782

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-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
Ahmad Hassan
2013-12-03 16:58:29 UTC
Permalink
Hi Andreas,

Thanks for the help. I think I figured out the cause of this problem. In
x86 system, e820 table tells the system which physical addresses are
available in the hardware. So I need to define proper entries in e826
dictionary inside FSConfig.py based on the defined memory controller
ranges. If I define three memory controller and configure their ranges in
e820, I get the following error. Please can someone expert in configuring
e820 table guide me how to fix this mapping issue? Thanks

BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 0000000010000000 (usable)
BIOS-e820: 0000000280000000 - 00000002c0000000 (usable)
BIOS-e820: 0000003100000000 - 0000003140000000 (usable)
end_pfn_map = 51642368
kernel direct mapping tables up to 3140000000 @ 100000-1c6000
DMI 2.5 present.
Zone PFN ranges:
DMA 0 -> 4096
DMA32 4096 -> 1048576
Normal 1048576 -> 51642368
early_node_map[4] active PFN ranges
0: 0 -> 159
0: 256 -> 65536
0: 2621440 -> 2883584
0: 51380224 -> 51642368
bootmem alloc of 2891972608 bytes failed!
Kernel panic - not syncing: Out of memory
PANIC: early exception rip ffffffff80215ca0 error 0 cr2 ffffffffff5fd030

Best Regards, Hassan
Post by Andreas Hansson
Hi Hassan,
Someone skilled in the assumptions of x86 memory layout may be able to
help you. I doubt there is an easy fix, but I could be wrong.
For ARM it should not be a problem to have this “segmented” memory.
Currently the gem5 ARM Linux System assumes a single range presented to the
OS, but this could easily be fixed (see LinuxArmSystem::initState). If you
take the plunge and go this route please share the patch on RB.
Thanks,
Andreas
Date: Monday, 2 December 2013 16:18
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously
Hi Andreas,
Please may I ask if you are experiencing the similar errors if you
define a second main memory controller beyond IO physical address ranges?
Would this be happening or this is completely an undesired behavior?
If Linux always need contiguous physical address range for multiple
memory controllers then is it possible to move IO address range from 3GB
start address to something 128GB starting address and then define two main
memory controllers that share the physical address range of 0GB to 128GB to
have 128 GB RAM capacity please?
In another attempt, I tried to move the first main memory controller
starting from 0GB to 10GB but it doesn't work because linux is accessing
memory between 0 to 128MB address range.
Thanks again for your help.
Best Regards, Hassan
Post by Ahmad Hassan
Hi Andreas,
To make sure it is not caused by my local changes, I just cloned the
self.physmem = SimpleDDR3(range = AddrRange(start="0GB",
size="2GB"))
self.physmem2 = SimpleDDR3(range = AddrRange(start="50GB",size="1GB"))
self.mem_ranges = [self.physmem.range,self.physmem2.range]
Again, I see the same error where linux boot-up fails while accessing
physical address: 3217031168. It seems that guest OS assumes that All 3GB
space is contiguous.
I don't know why it worked last week.
Thanks for the help.
Best Regards, Hassan
Post by Ahmad Hassan
Hi Andreas,
I assume so. I get this 'segmentation fault' while booting
linux: ./build/X86/gem5.opt configs/example/fs.py
--kernel=x86_64-vmlinux-2.6.22.9.smp
But I think, I booted the linux last week with similar configuration
and I think it worked fine. It seems bit strange to me that I am seeing
this segmentation fault now.
Best Regards, Hassan
Post by Andreas Hansson
Hi Hassan,
What is it that is assuming that the memory is contiguous? The guest OS?
Andreas
Date: Thursday, 28 November 2013 06:43
Subject: Re: [gem5-users] Running two SimpleDram instances
simulataniously
Hi Andreas,
self.dram2_ctl = SimpleDDR3(range =
AddrRange(start='0MB',size='3GB'))
self.dram1_ctl = SimpleDDR3(range =
AddrRange(start='10GB',size='16GB'))
But I am getting exception in findPort method where it raises because
it tries to access physical address 6438256672 for membus
DPRINTF(BusAddrRanges, "Unable to find destination for addr %#llx, "
"will use default port\n", addr);
As a result of that, I get segmentation fault during memcpy operation
in abstract_mem.cc:access
This error is happening because system is assuming that all the 19GB of
physical memory is contiguous. Please can you advise me how to fix this.
Thanks.
Best Regards, Hassan
Hi Ahmad,
If you change the bus code then every bus in the system will do
this, including the I/O bus. I suspect this is the reason for your error.
You can keep on the hackish path and add a name check to only do this for
the membus (or add a parameter to the bus and change the MemBus instance),
or preferably get of the hackish path and rely on physical addresses and
sort out your “placement” by assigning the appropriate physical addresses
in your TLBs (or preferably in the OS).
Red pill or blue pill.
Andreas
Date: Thursday, 31 October 2013 16:51
Subject: Re: [gem5-users] Running two SimpleDram instances
simulataniously
Hi Andreas,
DDR3 memory controller: Port ID 0 //2GB capacity
DDR2 memory controller: Port ID 1 //1GB capacity
When the packet comes into bus.cc:findPort then it searches for
packet's physical address in the registered portMap of address ranges and
returns the appropriate port ID. I don't want to do this. Instead, I want
to select port based on the virtual address. I have list of virtual
addresses say V=[V1....Vn] and I want to redirect all the packets with
virtual address within set 'V' to DDR3 Port 0 and all other memory packets
to the DDR2 port 1.
if (search(V, pkt->req->getVaddr()) == true)
dest_id = 0;
else
dest_id = 1;
After that, abstract_mem.cc:access complained that the packet
address doesn't belong to the range of PORT '1'. Just as a quick hack, I
old: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
new: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - 0; // Port ID 0
range starts with '0'
Now the linux starts booting but during the half way, it throws this
cmos assertion. Please can you suggest the clean or right way of
implementing what I am trying to achieve.
Thanks a lot
kind Regards, Ahmad
Hi Ahmad,
I could be wrong, but judging by your mail, I get the impression
that you’re overriding the address decoding. That is essentially saying “If
I send requests for address X to address Y, why do things not work?”. I
would be very surprised if it did, as two addresses will now map to the
same location :-). Perhaps I’m not understanding what you’ve changed.
Andreas
Date: Thursday, 31 October 2013 16:12
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously
HI Andreas,
I have connected two memory controllers and I can see the following
Adding range [0 : 2147483647] for id 0 system.membus // 2GB memory
Adding range [2147483648 : 3221225471] for id 1 system.membus
//1GB memroy
Inside findPort method of bus.cc, if I assign the packet of port id
'0' to port id '1' then I get the following assertion error. This happens
gem5.opt: build/X86/dev/x86/cmos.cc:70: virtual Tick
X86ISA::Cmos::write(PacketPtr): Assertion `pkt->getSize() == 1' failed.
Please do you know what is causing that? Also I had to disable
assertion in abstract memory which validates that the packet's physical
address in with in the range of memory controller.
Thanks.
kind Regards, Ahmad
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Registered in England & Wales, Company No: 2557590
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9NJ, Registered in England & Wales, Company No: 2548782
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Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1
9NJ, Registered in England & Wales, Company No: 2548782
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ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
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Ahmad Hassan
2013-12-04 10:39:22 UTC
Permalink
Hi Andreas,

Segmented controllers works on x86 system now. I can boot Linux with 147GB
memory. i have three controllers as:

self.physmem1 = SimpleDDR3(range = AddrRange(start='0MB',size='3GB'))
self.physmem2 = SimpleDDR3(range = AddrRange(start='8GB',size='128GB'))
self.physmem3 = SimpleDDR3(range =
AddrRange(start='196GB',size='16GB'))

For above, e820 table should be:

self.e820_table.entries = \
[
X86E820Entry(addr = 0, size = '639kB', range_type = 1),
X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
X86E820Entry(addr = 0x100000, size = '%dB' % (0xc0000000 -
0x100000), range_type = 1),
X86E820Entry(addr = 0x200000000, size = '128GB', range_type = 1),
X86E820Entry(addr = 0x3100000000, size = '16GB', range_type = 1)
]

Please can you tell me when the Linux on gem5 would go on swapping with
above configuration? Would that be when RAM on actual physical hardware
will run out? My physical system has 4GB RAM.

Second, what abstract_mem.c:access is doing. Where does these memcpy
operations copying data? Do they affect the latency/timing/power number of
a memory controller?

Thanks.

Best Regards, Hassan
Post by Ahmad Hassan
Hi Andreas,
Thanks for the help. I think I figured out the cause of this problem. In
x86 system, e820 table tells the system which physical addresses are
available in the hardware. So I need to define proper entries in e826
dictionary inside FSConfig.py based on the defined memory controller
ranges. If I define three memory controller and configure their ranges in
e820, I get the following error. Please can someone expert in configuring
e820 table guide me how to fix this mapping issue? Thanks
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 0000000010000000 (usable)
BIOS-e820: 0000000280000000 - 00000002c0000000 (usable)
BIOS-e820: 0000003100000000 - 0000003140000000 (usable)
end_pfn_map = 51642368
DMI 2.5 present.
DMA 0 -> 4096
DMA32 4096 -> 1048576
Normal 1048576 -> 51642368
early_node_map[4] active PFN ranges
0: 0 -> 159
0: 256 -> 65536
0: 2621440 -> 2883584
0: 51380224 -> 51642368
bootmem alloc of 2891972608 bytes failed!
Kernel panic - not syncing: Out of memory
PANIC: early exception rip ffffffff80215ca0 error 0 cr2 ffffffffff5fd030
Best Regards, Hassan
Post by Andreas Hansson
Hi Hassan,
Someone skilled in the assumptions of x86 memory layout may be able to
help you. I doubt there is an easy fix, but I could be wrong.
For ARM it should not be a problem to have this “segmented” memory.
Currently the gem5 ARM Linux System assumes a single range presented to the
OS, but this could easily be fixed (see LinuxArmSystem::initState). If you
take the plunge and go this route please share the patch on RB.
Thanks,
Andreas
Date: Monday, 2 December 2013 16:18
Subject: Re: [gem5-users] Running two SimpleDram instances
simulataniously
Hi Andreas,
Please may I ask if you are experiencing the similar errors if you
define a second main memory controller beyond IO physical address ranges?
Would this be happening or this is completely an undesired behavior?
If Linux always need contiguous physical address range for multiple
memory controllers then is it possible to move IO address range from 3GB
start address to something 128GB starting address and then define two main
memory controllers that share the physical address range of 0GB to 128GB to
have 128 GB RAM capacity please?
In another attempt, I tried to move the first main memory controller
starting from 0GB to 10GB but it doesn't work because linux is accessing
memory between 0 to 128MB address range.
Thanks again for your help.
Best Regards, Hassan
Post by Ahmad Hassan
Hi Andreas,
To make sure it is not caused by my local changes, I just cloned the
self.physmem = SimpleDDR3(range = AddrRange(start="0GB", size="2GB"))
self.physmem2 = SimpleDDR3(range =
AddrRange(start="50GB",size="1GB"))
self.mem_ranges = [self.physmem.range,self.physmem2.range]
Again, I see the same error where linux boot-up fails while accessing
physical address: 3217031168. It seems that guest OS assumes that All 3GB
space is contiguous.
I don't know why it worked last week.
Thanks for the help.
Best Regards, Hassan
Post by Ahmad Hassan
Hi Andreas,
I assume so. I get this 'segmentation fault' while booting
linux: ./build/X86/gem5.opt configs/example/fs.py
--kernel=x86_64-vmlinux-2.6.22.9.smp
But I think, I booted the linux last week with similar configuration
and I think it worked fine. It seems bit strange to me that I am seeing
this segmentation fault now.
Best Regards, Hassan
Post by Andreas Hansson
Hi Hassan,
What is it that is assuming that the memory is contiguous? The guest OS?
Andreas
Date: Thursday, 28 November 2013 06:43
Subject: Re: [gem5-users] Running two SimpleDram instances
simulataniously
Hi Andreas,
self.dram2_ctl = SimpleDDR3(range =
AddrRange(start='0MB',size='3GB'))
self.dram1_ctl = SimpleDDR3(range =
AddrRange(start='10GB',size='16GB'))
But I am getting exception in findPort method where it raises
because it tries to access physical address 6438256672 for membus
DPRINTF(BusAddrRanges, "Unable to find destination for addr %#llx, "
"will use default port\n", addr);
As a result of that, I get segmentation fault during memcpy
operation in abstract_mem.cc:access
This error is happening because system is assuming that all the 19GB
of physical memory is contiguous. Please can you advise me how to fix this.
Thanks.
Best Regards, Hassan
Hi Ahmad,
If you change the bus code then every bus in the system will do
this, including the I/O bus. I suspect this is the reason for your error.
You can keep on the hackish path and add a name check to only do this for
the membus (or add a parameter to the bus and change the MemBus instance),
or preferably get of the hackish path and rely on physical addresses and
sort out your “placement” by assigning the appropriate physical addresses
in your TLBs (or preferably in the OS).
Red pill or blue pill.
Andreas
Date: Thursday, 31 October 2013 16:51
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously
Hi Andreas,
DDR3 memory controller: Port ID 0 //2GB capacity
DDR2 memory controller: Port ID 1 //1GB capacity
When the packet comes into bus.cc:findPort then it searches for
packet's physical address in the registered portMap of address ranges and
returns the appropriate port ID. I don't want to do this. Instead, I want
to select port based on the virtual address. I have list of virtual
addresses say V=[V1....Vn] and I want to redirect all the packets with
virtual address within set 'V' to DDR3 Port 0 and all other memory packets
to the DDR2 port 1.
if (search(V, pkt->req->getVaddr()) == true)
dest_id = 0;
else
dest_id = 1;
After that, abstract_mem.cc:access complained that the packet
address doesn't belong to the range of PORT '1'. Just as a quick hack, I
old: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
new: uint8_t *hostAddr = pmemAddr + pkt->getAddr() - 0; // Port ID
0 range starts with '0'
Now the linux starts booting but during the half way, it throws
this cmos assertion. Please can you suggest the clean or right way of
implementing what I am trying to achieve.
Thanks a lot
kind Regards, Ahmad
Hi Ahmad,
I could be wrong, but judging by your mail, I get the impression
that you’re overriding the address decoding. That is essentially saying “If
I send requests for address X to address Y, why do things not work?”. I
would be very surprised if it did, as two addresses will now map to the
same location :-). Perhaps I’m not understanding what you’ve changed.
Andreas
Date: Thursday, 31 October 2013 16:12
Subject: Re: [gem5-users] Running two SimpleDram instances simulataniously
HI Andreas,
I have connected two memory controllers and I can see the
Adding range [0 : 2147483647] for id 0 system.membus // 2GB memory
Adding range [2147483648 : 3221225471] for id 1 system.membus
//1GB memroy
Inside findPort method of bus.cc, if I assign the packet of port
id '0' to port id '1' then I get the following assertion error. This
gem5.opt: build/X86/dev/x86/cmos.cc:70: virtual Tick
X86ISA::Cmos::write(PacketPtr): Assertion `pkt->getSize() == 1' failed.
Please do you know what is causing that? Also I had to disable
assertion in abstract memory which validates that the packet's physical
address in with in the range of memory controller.
Thanks.
kind Regards, Ahmad
-- IMPORTANT NOTICE: The contents of this email and any attachments
are confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1
9NJ, Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
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are confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1
9NJ, Registered in England & Wales, Company No: 2548782
_______________________________________________
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recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1
9NJ, Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
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confidential and may also be privileged. If you are not the intended
recipient, please notify the sender immediately and do not disclose the
contents to any other person, use it for any purpose, or store or copy the
information in any medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
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