[gem5-users] x86 floating point instruction

Discussion:

Tariq Azmy

2018-05-23 21:07:30 UTC

Hi,

I wrote simple code that does simple floating point multiplication and
division operation and from the assembly, I can see there are MULSS and
DIVSS instructions. But after I ran the simulation on gem5 and looked at
the stat.txt, I can only see the entries in
system.cpu.iq.FU_type_0::FloatAdd, where as the entries in FloatMul and
FloatDiv remains 0.

If I understand correctly, these stats refer to the micro-ops. Does that
mean the MULSS and DIVSS instruction are broken down and executed with
floating point Add?

Thanks

Gabe Black

2018-05-23 23:13:41 UTC

Permalink

I'm confident they aren't implemented with floating point add. It's likely
either that the microops are misclassified, or they're unimplemented and
printing a warning, but the fact that they don't actually do any math isn't
impacting your program for whatever reason. I'll take a quick look.

Gabe

Post by Tariq Azmy
Hi,
I wrote simple code that does simple floating point multiplication and
division operation and from the assembly, I can see there are MULSS and
DIVSS instructions. But after I ran the simulation on gem5 and looked at
the stat.txt, I can only see the entries in system.cpu.iq.FU_type_0::FloatAdd,
where as the entries in FloatMul and FloatDiv remains 0.
If I understand correctly, these stats refer to the micro-ops. Does that
mean the MULSS and DIVSS instruction are broken down and executed with
floating point Add?
Thanks
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Gabe Black

2018-05-23 23:51:32 UTC

Permalink

Yep, those microops aren't given a operand class, and so the isa parser is
guessing and making the FloatAddOp. I haven't really tested this beyond
making sure it compiles, but here's a patch that might get this working for
you.

https://gem5-review.googlesource.com/c/public/gem5/+/10541

Gabe

Post by Gabe Black
I'm confident they aren't implemented with floating point add. It's likely
either that the microops are misclassified, or they're unimplemented and
printing a warning, but the fact that they don't actually do any math isn't
impacting your program for whatever reason. I'll take a quick look.
Gabe

Tariq Azmy

2018-05-24 00:56:31 UTC

Permalink

Thanks Gabe. Yeah it does not impact the program but it's just that the
statistic is incorrect.

By the way, I applied the patch and stats now shows correct micro-ops
entries.

Appreciate your help. Thanks again

Post by Gabe Black
Yep, those microops aren't given a operand class, and so the isa parser is
guessing and making the FloatAddOp. I haven't really tested this beyond
making sure it compiles, but here's a patch that might get this working for
you.
https://gem5-review.googlesource.com/c/public/gem5/+/10541
Gabe

Post by Gabe Black
I'm confident they aren't implemented with floating point add. It's
likely either that the microops are misclassified, or they're unimplemented
and printing a warning, but the fact that they don't actually do any math
isn't impacting your program for whatever reason. I'll take a quick look.
Gabe

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gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Jason Lowe-Power

2018-05-24 14:52:49 UTC

Permalink

Hi Tariq,

It wold be great if you could review Gabe's patch on gerrit. Since it works
for you, giving it a +1 or a +2 would be appropriate.

Cheers,
Jason

Post by Tariq Azmy
Thanks Gabe. Yeah it does not impact the program but it's just that the
statistic is incorrect.
By the way, I applied the patch and stats now shows correct micro-ops
entries.
Appreciate your help. Thanks again

Post by Gabe Black
Yep, those microops aren't given a operand class, and so the isa parser
is guessing and making the FloatAddOp. I haven't really tested this beyond
making sure it compiles, but here's a patch that might get this working for
you.
https://gem5-review.googlesource.com/c/public/gem5/+/10541
Gabe

Post by Gabe Black
I'm confident they aren't implemented with floating point add. It's
likely either that the microops are misclassified, or they're unimplemented
and printing a warning, but the fact that they don't actually do any math
isn't impacting your program for whatever reason. I'll take a quick look.
Gabe

Post by Tariq Azmy
Hi,
I wrote simple code that does simple floating point multiplication and
division operation and from the assembly, I can see there are MULSS and
DIVSS instructions. But after I ran the simulation on gem5 and looked at
the stat.txt, I can only see the entries in
system.cpu.iq.FU_type_0::FloatAdd, where as the entries in FloatMul and
FloatDiv remains 0.
If I understand correctly, these stats refer to the micro-ops. Does
that mean the MULSS and DIVSS instruction are broken down and executed with
floating point Add?
Thanks
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Tariq Azmy

2018-05-25 21:12:41 UTC

Permalink

Hi Gabe, Jason,

Are those x86 SIMD SSE arithmetic instructions take only one cycle as
latency? I looked into the FuncUnitConfig.py and seems like the op lats for
the SIMD functional units are not defined, so I assumed it takes value of 1
by default.

I am not really familiar with x86 SIMD extension, so maybe this question is
more related to x86 ISA in general.

Thanks.

Post by Jason Lowe-Power
Hi Tariq,
It wold be great if you could review Gabe's patch on gerrit. Since it
works for you, giving it a +1 or a +2 would be appropriate.
Cheers,
Jason

Post by Gabe Black
Yep, those microops aren't given a operand class, and so the isa parser
is guessing and making the FloatAddOp. I haven't really tested this beyond
making sure it compiles, but here's a patch that might get this working for
you.
https://gem5-review.googlesource.com/c/public/gem5/+/10541
Gabe

Post by Gabe Black
I'm confident they aren't implemented with floating point add. It's
likely either that the microops are misclassified, or they're unimplemented
and printing a warning, but the fact that they don't actually do any math
isn't impacting your program for whatever reason. I'll take a quick look.
Gabe

Post by Tariq Azmy
Hi,
I wrote simple code that does simple floating point multiplication and
division operation and from the assembly, I can see there are MULSS and
DIVSS instructions. But after I ran the simulation on gem5 and looked at
the stat.txt, I can only see the entries in system.cpu.iq.FU_type_0::FloatAdd,
where as the entries in FloatMul and FloatDiv remains 0.
If I understand correctly, these stats refer to the micro-ops. Does
that mean the MULSS and DIVSS instruction are broken down and executed with
floating point Add?
Thanks
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Jason Lowe-Power

2018-05-28 16:09:02 UTC

Permalink

Hi Tariq,

It's up to you what you want the latency for SSE instructions to be. It
depends on what architecture you're simulating. Unfortunately, we currently
don't have any "known good" configurations for x86 cores so you'll have to
come up with your own :). Here's some examples of numbers you could use.
http://www.agner.org/optimize/instruction_tables.pdf

Cheers,
Jason

Post by Tariq Azmy
Hi Gabe, Jason,
Are those x86 SIMD SSE arithmetic instructions take only one cycle as
latency? I looked into the FuncUnitConfig.py and seems like the op lats for
the SIMD functional units are not defined, so I assumed it takes value of 1
by default.
I am not really familiar with x86 SIMD extension, so maybe this question
is more related to x86 ISA in general.
Thanks.

Post by Jason Lowe-Power
Hi Tariq,
It wold be great if you could review Gabe's patch on gerrit. Since it
works for you, giving it a +1 or a +2 would be appropriate.
Cheers,
Jason

Post by Gabe Black
Yep, those microops aren't given a operand class, and so the isa parser
is guessing and making the FloatAddOp. I haven't really tested this beyond
making sure it compiles, but here's a patch that might get this working for
you.
https://gem5-review.googlesource.com/c/public/gem5/+/10541
Gabe

Post by Gabe Black
I'm confident they aren't implemented with floating point add. It's
likely either that the microops are misclassified, or they're unimplemented
and printing a warning, but the fact that they don't actually do any math
isn't impacting your program for whatever reason. I'll take a quick look.
Gabe

Post by Tariq Azmy
Hi,
I wrote simple code that does simple floating point multiplication
and division operation and from the assembly, I can see there are MULSS and
DIVSS instructions. But after I ran the simulation on gem5 and looked at
the stat.txt, I can only see the entries in
system.cpu.iq.FU_type_0::FloatAdd, where as the entries in FloatMul and
FloatDiv remains 0.
If I understand correctly, these stats refer to the micro-ops. Does
that mean the MULSS and DIVSS instruction are broken down and executed with
floating point Add?
Thanks
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Tariq Azmy

2018-05-28 18:17:51 UTC

Permalink

Thanks Jason. I also came across the same document earlier but I just
wanted to ask about this in general.

Post by Jason Lowe-Power
Hi Tariq,
It's up to you what you want the latency for SSE instructions to be. It
depends on what architecture you're simulating. Unfortunately, we currently
don't have any "known good" configurations for x86 cores so you'll have to
come up with your own :). Here's some examples of numbers you could use.
http://www.agner.org/optimize/instruction_tables.pdf
Cheers,
Jason

Post by Jason Lowe-Power
Hi Tariq,
It wold be great if you could review Gabe's patch on gerrit. Since it
works for you, giving it a +1 or a +2 would be appropriate.
Cheers,
Jason

Post by Gabe Black
Yep, those microops aren't given a operand class, and so the isa
parser is guessing and making the FloatAddOp. I haven't really tested this
beyond making sure it compiles, but here's a patch that might get this
working for you.
https://gem5-review.googlesource.com/c/public/gem5/+/10541
Gabe

Post by Gabe Black
I'm confident they aren't implemented with floating point add. It's
likely either that the microops are misclassified, or they're unimplemented
and printing a warning, but the fact that they don't actually do any math
isn't impacting your program for whatever reason. I'll take a quick look.
Gabe

Post by Tariq Azmy
Hi,
I wrote simple code that does simple floating point multiplication
and division operation and from the assembly, I can see there are MULSS and
DIVSS instructions. But after I ran the simulation on gem5 and looked at
the stat.txt, I can only see the entries in system.cpu.iq.FU_type_0::FloatAdd,
where as the entries in FloatMul and FloatDiv remains 0.
If I understand correctly, these stats refer to the micro-ops. Does
that mean the MULSS and DIVSS instruction are broken down and executed with
floating point Add?
Thanks
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users