[gem5-users] Any recommendation of ARM HPI configuration

[杜东]

Hi guys,

I am using GEM5 ARM with the Minor CPU (specifically, HPI mode).
The default configuration is :
Core: 4GHz
TLB: 256 entries I/D TLB
L1 I/D cache: 1 cycle (data/tag/response)
L2 I/D cache: 13 cycles for data and tag access
memory type: DDR3_1600_8x8.

This default configuration seems too great?
I am not sure whether real devices can achieve the performance, especially 1 cycle L1 cache access.

So do you have any recommendation on the configurations?
Any comments are welcomed!

Dong

[Ciro Santilli]

I recommend that you pick a specific board of interest, and then look for SoC / DRAM specs online.

________________________________
From: gem5-users <gem5-users-***@gem5.org> on behalf of ¶Å¶« <***@sjtu.edu.cn>
Sent: Monday, December 3, 2018 12:36 PM
To: m5-users
Subject: [gem5-users] Any recommendation of ARM HPI configuration

Hi guys,

I am using GEM5 ARM with the Minor CPU (specifically, HPI mode).
The default configuration is :
Core: 4GHz
TLB: 256 entries I/D TLB
L1 I/D cache: 1 cycle (data/tag/response)
L2 I/D cache: 13 cycles for data and tag access
memory type: DDR3_1600_8x8.

This default configuration seems too great?
I am not sure whether real devices can achieve the performance, especially 1 cycle L1 cache access.

So do you have any recommendation on the configurations?
Any comments are welcomed!

Dong
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http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[Georgios S. Bousdras]

Hi,

You need to know what are you going to test (perfomance/power).
Take in to account that different architectures support different applications.
Define the demands of the system and then do what Ciro said, find an existed SoC which match your requirements and create your processor similar to it.

Best Regards,
Georgios Bousdras
PhD Researchers - Embedded Systems
BEAMS - ULB

Post by 杜东
Hi guys,
I am using GEM5 ARM with the Minor CPU (specifically, HPI mode).
Core: 4GHz
TLB: 256 entries I/D TLB
L1 I/D cache: 1 cycle (data/tag/response)
L2 I/D cache: 13 cycles for data and tag access
memory type: DDR3_1600_8x8.
This default configuration seems too great?
I am not sure whether real devices can achieve the performance, especially 1 cycle L1 cache access.
So do you have any recommendation on the configurations?
Any comments are welcomed!
Dong
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[杜东]

Hi,
Thanks for Georgios and Crio's comments!
I want to test the performance, and wish the result could be close to real devices.
I have searched for several SoC (ARMv8) from the link (https://en.wikipedia.org/wiki/Comparison_of_ARMv8-A_cores).
While the frequency and cache/TLB size are easy to figure out, I can not found official specs to describe the Cache access latency.
I found a website, which records a tested Cortex-A57 result in (https://www.7-cpu.com/cpu/Cortex-A57.html).

I put the result here (just as a reference for others may need):
L1 Data Cache Latency = 4 cycles for simple access via pointer
L1 Data Cache Latency = 5 cycles for access with complex address calculation (size_t n, *p; n = p[n]).
L2 Cache Latency = 18 cycles

Dong


----- Original Message -----
From: "Georgios S. Bousdras" <***@ulb.ac.be>
To: "gem5 users mailing list" <gem5-***@gem5.org>
Sent: Monday, December 3, 2018 8:55:47 PM
Subject: Re: [gem5-users] Any recommendation of ARM HPI configuration

Hi,

You need to know what are you going to test (perfomance/power).
Take in to account that different architectures support different applications.
Define the demands of the system and then do what Ciro said, find an existed SoC which match your requirements and create your processor similar to it.

Best Regards,
Georgios Bousdras
PhD Researchers - Embedded Systems
BEAMS - ULB

Post by 杜东
Hi guys,
I am using GEM5 ARM with the Minor CPU (specifically, HPI mode).
Core: 4GHz
TLB: 256 entries I/D TLB
L1 I/D cache: 1 cycle (data/tag/response)
L2 I/D cache: 13 cycles for data and tag access
memory type: DDR3_1600_8x8.
This default configuration seems too great?
I am not sure whether real devices can achieve the performance, especially 1 cycle L1 cache access.
So do you have any recommendation on the configurations?
Any comments are welcomed!
Dong
_______________________________________________
gem5-users mailing list
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users