Discussion:
How to support multiple memory requests in a single instruction
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杜东
2018-11-15 11:08:37 UTC
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Hi guys,
I am trying to add a new instructions in Gem5 ARM (FS mode) which can support loading from two memory addresses into two registers. (The memory addresses are already stored in two system registers).
I want to implement it in the Minor CPU (specifically, HPI mode).
During developing, I met one problem:

The memory load operation implemented in Minor CPU requires the instruction to invoke "initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);" in initiateAcc stage, and invoke "getMem(pkt, Mem, traceData);" in the completeAcc stage.
The completeAcc will get one packet from pipeline and then read the data from the packet.
It seems I need to modify the Minor CPU's code for multiple memory load...

Any advices about this?

Thanks a lot!
Andreas Sandberg
2018-11-15 11:40:56 UTC
Permalink
Hi,

I would suggest having a look at the SVE support that Giacomo Gabrielly
posted for review a while back. There is support for SVE load/store
structure instructions [1] there that sound very similar to what you
want to achieve.

Cheers,
Andreas

[1] https://gem5-review.googlesource.com/c/public/gem5/+/13524
Post by 杜东
Hi guys,
I am trying to add a new instructions in Gem5 ARM (FS mode) which can support loading from two memory addresses into two registers. (The memory addresses are already stored in two system registers).
I want to implement it in the Minor CPU (specifically, HPI mode).
The memory load operation implemented in Minor CPU requires the instruction to invoke "initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);" in initiateAcc stage, and invoke "getMem(pkt, Mem, traceData);" in the completeAcc stage.
The completeAcc will get one packet from pipeline and then read the data from the packet.
It seems I need to modify the Minor CPU's code for multiple memory load...
Any advices about this?
Thanks a lot!
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