Discussion:
[gem5-users] config starter_fs.py with aarch32
Andreas Konopik
2018-07-17 18:00:03 UTC
Permalink
Hello,

i encounter a problem booting linux in fs mode with edited
gem5/configs/example/arm/starter_fs.py file.
I changed nothing more than:

* default_dist_version = ''
* default_kernel = 'vmlinux.vexpress_gem5_v1'
* default_disk = 'linux-aarch32-ael.img'
* added "o3" to cpu_types with DerivO3CPU
* and deleted a dot in the dtb_file string

Now called fs32_mp.py

with exported M5_PATH=$HOME/gem5/full_system/aarch-system-20180409
my commandline is:

~/gem5/build/ARM/gem5.opt ~/gem5/configs/example/arm/fs32_mp.py
--num-cores 2 --cpu o3

The config finds all relevant files needed to boot up linux, but ends up
with a kernel panic and is unable to boot.

Global frequency set at 1000000000000 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address
range assigned (2048 Mbytes)
info: kernel located at:
~/gem5/full_system/aarch-system-20180409/binaries/vmlinux.vexpress_emm
Listening for system connection on port 5910
Listening for system connection on port 3466
0: system.remote_gdb: listening for remote gdb on port 7040
0: system.remote_gdb: listening for remote gdb on port 7041
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file:
~/gem5/full_system/aarch-system-20180409/binaries/armv7_gem5_v1_2cpu.dtb
at address 0x88000000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue @ 0.  Starting simulation...
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
warn:   instruction 'mcr icimvau' unimplemented
warn:   instruction 'mcr bpiallis' unimplemented
warn:   instruction 'mcr icialluis' unimplemented
1102541000: system.terminal: attach terminal 0
info: Dumping kernel dmesg buffer to system.dmesg...
warn: Kernel oops in guest
info: Dumping kernel dmesg buffer to system.dmesg...
warn: Kernel panic in simulated kernel

Maybe i have to change the kernel entry address, but don't know to which
address.
I also attached system.dmesg output.

Thanks for your help!

regards,

Andreas Konopik
Ciro Santilli
2018-07-17 20:01:20 UTC
Permalink
Does it work if you undo the changes you've made and just use starter_fs.py?

Are there any terminal messages in system.dmesg?
Post by Andreas Konopik
Hello,
i encounter a problem booting linux in fs mode with edited
gem5/configs/example/arm/starter_fs.py file.
- default_dist_version = ''
- default_kernel = 'vmlinux.vexpress_gem5_v1'
- default_disk = 'linux-aarch32-ael.img'
- added "o3" to cpu_types with DerivO3CPU
- and deleted a dot in the dtb_file string
Now called fs32_mp.py
with exported M5_PATH=$HOME/gem5/full_system/aarch-system-20180409
~/gem5/build/ARM/gem5.opt ~/gem5/configs/example/arm/fs32_mp.py
--num-cores 2 --cpu o3
The config finds all relevant files needed to boot up linux, but ends up
with a kernel panic and is unable to boot.
Global frequency set at 1000000000000 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (2048 Mbytes)
info: kernel located at: ~/gem5/full_system/aarch-
system-20180409/binaries/vmlinux.vexpress_emm
Listening for system connection on port 5910
Listening for system connection on port 3466
0: system.remote_gdb: listening for remote gdb on port 7040
0: system.remote_gdb: listening for remote gdb on port 7041
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: ~/gem5/full_system/aarch-system-20180409/binaries/armv7_gem5_v1_2cpu.dtb
at address 0x88000000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
1102541000: system.terminal: attach terminal 0
info: Dumping kernel dmesg buffer to system.dmesg...
warn: Kernel oops in guest
info: Dumping kernel dmesg buffer to system.dmesg...
warn: Kernel panic in simulated kernel
Maybe i have to change the kernel entry address, but don't know to which
address.
I also attached system.dmesg output.
Thanks for your help!
regards,
Andreas Konopik
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